Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis

Tanizawa, Motoaki; Ohbayashi, S.; Okagaki, Takeshi; Sonoda, Keiichiro; Eikyu, K.; Hirano, Y.; Ishikawa, K.; Tsuchiya, O.; Inoue, Yasuo

doi:10.1109/vlsit.2010.5556184

Cited by 37 publications

(36 citation statements)

References 1 publication

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“…This held true even if unusually large values for the RTN amplitude had been consistently reported on some devices, together with complex time behaviors [79,82,[87][88][89], that seemed to defy Equation (2). When Flash memories made a large quantity of data readily available, making it possible to pinpoint and study anomalous behaviors occurring with extremely low probability, larger and larger fluctuation amplitudes emerged [90,91], and RTN became a serious reliability constraint in static random-access [92][93][94] and Flash memories [90,91,[95][96][97][98][99], prompting an intensive research effort to understand its root cause and impact on memory array operation. An example of the relevance of RTN is shown in Figure 4, where results obtained on a selected decananometer Flash cell are reported [91]: current fluctuations up to 60% were detected, which cannot be explained with the above theory.…”

Section: Rtn Amplitudementioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Section: Rtn Amplitudementioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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“…In [27], Fan, et.al present an analysis of the impact of V th variation in FinFET device based SRAM and logic cells. Statistical and circuit techniques have been proposed to characterize RTN at the device level [28] and predict its impact on stability of SRAM cells [29]. In this section, we present an analysis of A.…”

Section: Impact Of Random Telegraph Noise On Sram Testingmentioning

confidence: 99%

Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array

Suresh

Kundu

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Static Random Access Memories (SRAM) are a major constituent in high performance microprocessors and systems-on-a-chip (SoC). With scaling of technology, manufacturing process variations in SRAMs are of significant concern. SRAM cells that are marginal due to process variations suffer from stability issues where random thermal noise and random telegraph noise (RTN) become determinant in memory state. This introduces uncertainty in testing, where passing a test does not necessarily mean that SRAM is good. A marginal cell may pass testing, but fail during operation. To address this problem we introduce a new metric for probabilistic fault coverage. We present simulation methods for measuring such coverage and propose N-detect and multi-level WordLine (WL) voltage techniques to increase the detection probability of marginal cells. We demonstrate the benefit of these testing approaches on a sample SRAM array, designed in 32nm Predictive Technology Models. To simulate marginal cells, we oversample the tail of the process variations distribution. Transient noise simulations show that thermal noise can lead to a fault coverage loss of 20% and RTN can lead to a maximum fault coverage loss of up to 75%. N-detect technique achieves close to a 100% fault coverage at n=100 for thermal noise and n=70 for RTN. Multi-level WL technique requires 20-30mV boost in WL voltage during read test to achieve near ideal fault coverage at minimal yield loss. A combination of these techniques is shown to be effective in increasing fault coverage with a trade-off between test time and yield loss.

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“…In order to model the impact of RTN on digital circuits, the equivalent circuit technique is used [15], as shown in Fig. 3.…”

Section: B Rtn-induced V Th Fluctuation In Digital Circuitsmentioning

confidence: 99%

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

Luo

Wang

Cao

et al. 2012

2012 IEEE Computer Society Annual Symposium on VLSI

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Random telegraph noise (RTN) is one of the critical reliability concerns in nanoscale circuit design, and it is important to consider the impact of RTN on the circuits' temporal performance. This paper proposes a framework to evaluate the RTN-induced performance degradation and variation of digital circuits, and the evaluation results show that RTN can result in 54.4% degradation and 59.9% variation on the circuit delay at 16nm technology node. Power supply tuning and gate sizing techniques are investigated to demonstrate the impact of such circuit-level techniques on mitigating the RTN effect.

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Application of a statistical compact model for Random Telegraph Noise to scaled-SRAM Vmin analysis

Cited by 37 publications

References 1 publication

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits

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