Application of Automatic Parallelization to Modern Challenges of Scientific Computing Industries

Armstrong, B.; Eigenmann, Rudolf

doi:10.1109/icpp.2008.65

Cited by 6 publications

(5 citation statements)

References 9 publications

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“…Figure 13 shows our scalability speedups up to sixteen processors. Benchmark gamess, not measured, is notoriously difficult to parallelize [3] and we disambiguated only small-granularities loops that do not exhibit speedup, while applu exhibits two sequential loops that sum-up to 56% of sequential coverage and contain only sequential or smallgranularity inner loops, which do not contribute to speedup. SPEC2000 We observe that speedups do not scale well between 8 to 16 processors; this is likely because the machine has eight dual-core processors, and executing on both cores decreases the per-core bandwidth.…”

Section: Perfect Club Suite Resultsmentioning

confidence: 99%

“…The first rule says that a repeated (irreducible) subtraction from a summary should be reorganized as one subtraction between that summary and the union of the subtracted terms 3 . In Figure 8 we show intuitively that when A is included in neither B nor C, perhaps the union of B and C can simplify to a larger set in the arrayabstraction domain which includes A, thus enabling the extraction of a more meaningful predicate.…”

Section: Enabling Usr Transformation For Predicate Extractionmentioning

confidence: 99%

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Logical inference techniques for loop parallelization

Oancea

Rauchwerger

2012

SIGPLAN Not.

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This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S = ∅, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates (F(S) ⇒ S = ∅). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F (S)) into a sequence of sufficient-independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECT-CLUB and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers.

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Section: Perfect Club Suite Resultsmentioning

confidence: 99%

Section: Enabling Usr Transformation For Predicate Extractionmentioning

confidence: 99%

Logical inference techniques for loop parallelization

Oancea

Rauchwerger

2012

SIGPLAN Not.

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“…The strength of specialized kernel benchmarks is their ability to measure individual machine features by focusing on a particular system aspect. But observations of real application behavior are essential for assessing HPC technology [136], [137].…”

Section: ) Benchmarks Classificationmentioning

confidence: 99%

A Survey of Performance Tuning Techniques and Tools for Parallel Applications

Mustafa

2022

IEEE Access

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Automatic parallelization of sequential programs combined with autotuning is an alternative to manual parallelization. With wider research directions and the increased number of performance tuning tools that have been developed, it becomes harder to choose a particular tuning tool to use. This paper reviews the fundamentals of different performance optimization and tuning techniques. It also surveys many tuning frameworks and classifies them into different groups based on their criteria. Developing benchmarks for HPC and validating their accuracy have been demanding tasks for computer architects, researchers, and application developers. In addition to providing a survey of performance tuning tools, we also performed a detailed review of current benchmarks and discussed the requirements for future benchmarks. We performed a detailed comparison of these tuning tools based on other features such as speedup and infrastructure details. We believe that this paper will be a very useful resource for the parallel computing community, especially for early-stage parallel computing and performance researchers to gain exposure to the existing performance optimization options.

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“…The automatic parallelism has made great progress in numeric programs. But for general-purpose programs it can not exploit sufficient parallelism [7,8]. Since the irregular control flow and data flow in general-purpose programs make it hard for compiler to find enough threads which can execute in parallel without violating dependences.…”

Section: Introductionmentioning

confidence: 99%

Prophet: A Speculative Multi-threading Execution Model with Architectural Support Based on CMP

Dong

Zhao

Wei

et al. 2009

2009 International Conference on Scalable Computing and Communications; Eighth International Conference on Embedded Computing

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Abstract--Speculative Multithreading (SpMT) has been proposed as a perspective method to exploit Chip Multiprocessors (CMP) hardware's potential. It is a thread level speculation (TLS) model mainly depending on software and hardware co-design. This paper researches speculative thread-level parallelism of general-purpose programs and a speculative multi-threading execution model called Prophet is presented. The architectural support for Prophet execution model is designed based on CMP. In Prophet the inter-thread data dependences are predicted by pre-computation slice (p-slice) to reduce RAW violation. Prophet Multi-versioning Cache system along with thread state control mechanism in architectural support are utilized for buffering the speculative data, and a snooping bus based cache coherence protocol is used to detect data dependence violation. The simulation-based evaluation shows that the Prophet system could achieve significant speedup for general-purpose programs.

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Application of Automatic Parallelization to Modern Challenges of Scientific Computing Industries

Cited by 6 publications

References 9 publications

Logical inference techniques for loop parallelization

Logical inference techniques for loop parallelization

A Survey of Performance Tuning Techniques and Tools for Parallel Applications

Prophet: A Speculative Multi-threading Execution Model with Architectural Support Based on CMP

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