Application of EUV resolution enhancement techniques (RET) to optimize and extend single exposure bi-directional patterning for 7nm and beyond logic designs

Abstract

EUV lithography is uniquely positioned to extend single exposure solutions for critical imaging layers at the 7 nm technology node and beyond. In this work, we demonstrate the application of advanced EUV resolution enhancement techniques to enable bidirectional printing of 36 and 32 nm pitch standard logic cell and SRAM designs with 0.33 NA optics using an EUV OPC model. Prior work has highlighted the issues of pattern placement errors and image contrast loss due to the non-telecentricity that is inherent in EUV reflective imaging systems and masks. This work has also demonstrated utilizing asymmetric pupil to reduce the pattern placement error. It has been previously shown that there is a potential reduction in common process window due to through-pitch best focus shifts with non-optimized SRAF placement. In this paper, we demonstrate the use of: pattern placement error aware SMO, asymmetric illumination shape, and SRAF placement optimization to increase the overall common process window by as much as 40% compared to OPC only optimization. Consequently, we demonstrate the improved post-RET single patterning solution for 0.33 NA EUV bi-directional 7 nm node logic designs. We show that these techniques can achieve the required performance for MEEF, best focus shift across features, and ILS, which is known to be important for reducing stochastics and subsequent line-edge-roughness (LER).

The potential of EUV lithography

“…Lithographers are currently struggling to pattern 32 nm pitch lines and spaces with defect levels sufficiently low to be suitable for HVM. 4 With NA = 0.33, this represents patterning at k1 = 0.39, which is not particularly aggressive by the standards of optical lithography. It has long been understood that LER limits the patterning quality of tight pitches using EUV lithography, and in recent years there has been an improved understanding of the role of stochastic phenomena, such as resist inhomogeneities and photon shot noise, in limiting EUV lithographic capability.…”

Current challenges and opportunities for EUV lithography

“…This sensitivity to focus, particularly when there may be different planes for best focus for different features, indicates that EUV lithography will require very tight focus control. Independent of the mask 3D effects, it has also been found useful to have larger normalized image logslopes (NILs) than typically used for optical lithography, 20 in order to minimize LER and stochastic yield failures. This represents another constraint on OPC optimization.…”

Measurement of through-focus EUV pattern shifts using the SHARP actinic microscope

“…Since extreme ultraviolet (EUV) lithography at 13.5 nm wavelength is a potential patterning technology for high volume manufacturing of semiconductor devices at the 7 nm technology node and beyond, each of the techniques known to mitigate EUV 3D mask effects, including application of optical proximity corrections (OPC) to the geometric layout of the mask patterns to pre-correct the image deformations [5], utilization of a number of innovative source-mask optimization (SMO) resolution enhancement techniques [6][7], and development of EUV masks with alternatives to the conventional Ta-based absorber Mo/Si multilayer reflector film stack [8][9], needs to be benchmarked to experimental measurement data. stage to take consistent and accurate steps.…”