Application of LSTM Auto Encoder in Hardware Trojan Detection

Sumarsono, Alex; Masters, Zachary

doi:10.1109/ccwc57344.2023.10099121

Cited by 3 publications

References 11 publications

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A Siamese deep learning framework for efficient hardware Trojan detection using power side-channel data

Nasr,

Mohamed,

Elshenawy

et al. 2024

Sci Rep

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Hardware Trojans (HTs) are hidden threats embedded in the circuitry of integrated circuits (ICs), enabling unauthorized access, data theft, operational disruptions, or even physical harm. Detecting Hardware Trojans (HTD) is paramount for ensuring IC security. This paper introduces a novel Siamese neural network (SNN) framework for non-destructive HTD. The proposed framework can detect HTs by processing power side-channel signals without the need for a golden model of the IC. To obtain the best results, different neural network models such as Convolutional Neural Network (CNN), Gated Recurrent Unit (GRU), and Long Short-Term Memory (LSTM) are integrated individually with SNN. These models are trained on the extracted features from the Trojan Power & EM Side-Channel dataset. The results show that the Siamese LSTM model achieved the highest accuracy of 86.78%, followed by the Siamese GRU model with 83.59% accuracy and the Siamese CNN model with 73.54% accuracy. The comparison shows that of the proposed Siamese LSTM is a promising new approach for HTD and outperform the state-of-the-art methods.

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A Siamese deep learning framework for efficient hardware Trojan detection using power side-channel data

Nasr,

Mohamed,

Elshenawy

et al. 2024

Sci Rep

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Benchmarking for Hardware Security: Types, Design Levels, and Limitations

Bhatta,

Singh,

Amsaad

2023

2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs

Dofe,

Danesh,

et al. 2024

Cryptography

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Field-programmable gate arrays (FPGAs) offer the inherent ability to reconfigure at runtime, making them ideal for applications such as data centers, cloud computing, and edge computing. This reconfiguration, often achieved through remote access, enables efficient resource utilization but also introduces critical security vulnerabilities. An adversary could exploit this access to insert a dormant hardware trojan (HT) into the configuration bitstream, bypassing conventional security and verification measures. To address this security threat, we propose a supervised learning approach using deep recurrent neural networks (RNNs) for HT detection within FPGA configuration bitstreams. We explore two RNN architectures: basic RNN and long short-term memory (LSTM) networks. Our proposed method analyzes bitstream patterns, to identify anomalies indicative of malicious modifications. We evaluated the effectiveness on ISCAS 85 benchmark circuits of varying sizes and topologies, implemented on a Xilinx Artix-7 FPGA. The experimental results revealed that the basic RNN model showed lower accuracy in identifying HT-compromised bitstreams for most circuits. In contrast, the LSTM model achieved a significantly higher average accuracy of 93.5%. These results demonstrate that the LSTM model is more successful for HT detection in FPGA bitstreams. This research paves the way for using RNN architectures for HT detection in FPGAs, eliminating the need for time-consuming and resource-intensive reverse engineering or performance-degrading bitstream conversions.

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Application of LSTM Auto Encoder in Hardware Trojan Detection

Cited by 3 publications

References 11 publications

A Siamese deep learning framework for efficient hardware Trojan detection using power side-channel data

A Siamese deep learning framework for efficient hardware Trojan detection using power side-channel data

Benchmarking for Hardware Security: Types, Design Levels, and Limitations

Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs

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