Application performance improvement by exploiting process variability on FPGA devices

In-the-Field Mitigation of Process Variability for Improved FPGA Performance

“…To propose and develop an enhanced framework exploiting inter-and intra-die variability, as well as the guard-bands, to improve the FPGA performance, in-the-field, without modifying the vendor's tools. Compared to our previous publication [6], the main difference/extension of the current work lies in the exploitation of the intra-die variability. For this new and more challenging contribution, we employ our new statistical approach to analyze FPGA performance and we intensify the testing required.…”

“…The fundamental building block of our evaluation system is our custom sensor utilizing the well-established Ring Oscillator (RO) circuit [6]. In general, an RO consists of a chain of inverters forming an asynchronous loop as shown in the middle box of Fig.…”

“…Otherwise, time depends on the number of iterations searching for the highest error-free frequency (Algorithm 1) and could increase at most to 138À351 sec on Zynq's ARM A9. We note that this time can be significantly decreased, i.e., to less than one minute, by pruning the search space with adaptable frequency steps of 10À1 MHz (to perform a coarse-grain before the fine-grain search) [6].…”

“…In turn, these deviations translate to variations in speed and power consumption between supposedly identical dies (inter-die variability), or even inside a single die (intra-die variability). Indicatively, in a set of 28 nm chips, inter-and intra-die variability measures up to 17 and 7.7 percent, respectively [6].…”

“…Hence, for nominal operation, they ensure functional integrity even for the worst-case scenario of their entire production line. However, this pessimistic approach prevents the majority of the chips from utilizing their full capability and leads to a significant performance loss [6], [7], [8], [9], e.g., 80 percent of potential increase in operation frequency.…”