2020
DOI: 10.1145/3377403
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Application-Specific Arithmetic in High-Level Synthesis Tools

Abstract: This work studies hardware-specific optimization opportunities currently unexploited by high-level synthesis compilers. Some of these optimizations are specializations of floating-point operations that respect the usual semantics of the input program without changing the numerical result. Some other optimizations, locally triggered by the programmer thanks to a pragma, assume a different semantics, where floating-point code is interpreted as the specification of computation with real numbers. The compiler is t… Show more

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Cited by 10 publications
(5 citation statements)
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“…Incorporating CuFP into other projects is straightforward, as users can simply include a header file, ensuring effortless integration and user-friendly implementation. Its platform independence and open-source nature promote transparency and ease of debugging while maintaining performance levels 1 .…”
Section: Of 20mentioning
confidence: 99%
See 1 more Smart Citation
“…Incorporating CuFP into other projects is straightforward, as users can simply include a header file, ensuring effortless integration and user-friendly implementation. Its platform independence and open-source nature promote transparency and ease of debugging while maintaining performance levels 1 .…”
Section: Of 20mentioning
confidence: 99%
“…This abstraction allows a focus on system-level functionality, leading to faster design iterations. Moreover, HLS tools automate various optimization processes, reducing manual effort and accelerating development cycles [1].…”
Section: Introductionmentioning
confidence: 99%
“…The HLS compilers implement different optimization based on their particular Intermediate Representation (IR), such as pipelining or expressing data-level parallelism. However, they suffer from a lack of support for many other unexploited FPGAspecific optimizations for arithmetic operations [30] for instance. Hence, harnessing FPGAs' full potential via HLS tools requires knowledge of their architecture and a significant effort to adapt the application because OpenCL is not performance-portable from one platform to another.…”
Section: B Opencl Hlsmentioning
confidence: 99%
“…These compilers implement different optimization based on their particular intermediate representation (IR), such as pipelining or expressing data-level parallelism. However, they suffer from a lack of support for many other unexploited FPGA-specific optimizations for arithmetic operations [21] for instance. Hence, harnessing FPGAs' full potential via HLS tools requires knowledge of their architecture and a significant effort to adapt the application because it is not performance-portable.…”
Section: B Acceleration Platformmentioning
confidence: 99%