Application-specific clustered VLIW datapaths: early exploration on a parameterized design space

Abstract

Abstract-Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level parallelism inherent in many embedded media applications, while unlocking a variety of possible performance/cost tradeoffs. In this work, the authors propose a methodology to support early design space exploration of clustered VLIW datapaths, in the context of a specific target application. They argue that, due to the large size and complexity of the design space, the early design space exploration phase should consider only design space parameters that have a first-order impact on two key physical figures of merit: clock rate and power dissipation. These parameters were found to be: maximum cluster capacity, number of clusters, and bus (interconnect) capacity. Experimental validation of their design space exploration algorithm shows that a thorough exploration of the complex design space can be performed very efficiently in this abstract parameterized design space. Moreover, an empirical study carried out on a representative set of computation-intensive benchmarks suggests that "penalties" of clustered versus centralized datapaths are often minimal and that clustering indeed unlocks a variety of valuable design tradeoffs.

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

“…The challenges and future trends, like retargetable compilers and synthesis tools, were discussed in [8], and the first steps in finding standard methodologies and CAD tools have also been proposed [12], [13], to help designers in several tasks, including hardware/software partition and early design exploration. However a complete automated methodology is still far off.…”

Design space exploration for real-time embedded stream processors

“…Design space exploration has been studied for VLIW-based embedded processors [8,9] for performance and power. These techniques directly relate to a design exploration for a single cluster stream processor.…”

“…In order to model memory stalls and observe the sensitivity of the design to the stalls, we model the worst-case stall , is computed during the design exploration. There are other parameters in an embedded stream processor that can affect performance and need exploration such as the number of registers and pipelining depth of arithmetic units [2,8,9]. These parameters affect the ILP for a cluster and hence, indirectly affect the CDP.…”

Cluster assignment for high-performance embedded VLIW processors

“…The algorithm was originally designed to work with VLIW datapaths, specialized to execute time-critical kernels of embedded applications [Lapinskii et al 2002].…”

“…These include a register and code size-sensitive software pipelining algorithm for clustered VLIW machines [Akturan and Jacome 2001] and a design space exploration framework for clustered VLIW datapath configurations [Lapinskii et al 2002].…”