Application-specific DSP architecture for fast Fourier transform

Abstract

This paper presents ASDSP (Application-Specific Digital Signal Processor) instructions andtheir hardware architecture for high-speed FFT. The proposed instructions calculate a butterfly within two cycles. The proposed architecture employs a Data Processing Unit (DPU) supporting the instructions and an FFT Address Generation Unit (FAGU) automatically calculating the butterfly input and output data addresses. The proposed DPU has a smaller area than commercial DSP chips. Moreover, the number of FFT computation cycles is reduced by the proposed FAGU. The architecture has been modeled by the VHDL. We have used the UMC 0.25@standard cell library for logic synthesis. Performance comparisons show that the number of execution cycles is reduced over 10% and the size of the DPU decreases about 30% compared with Carmel DSP.

A hierarchical design of an application-specific instruction set processor for high-throughput FFT

“…Other DSPs like TI's TMS320c6X processor achieve good performance in embedded applications [4], while it uses 256-bit long instructions, which is not energy-efficient for domain-specific applications. As an intermediate design option between ASIC and general purpose DSP, applicationspecific instruction set processor (ASIP) has emerged in recent decades, which can offer both good flexibility with base core software control and high throughput with hardware acceleration, suitable for FFT algorithms [5].…”

Design of an application-specific instruction set processor for high-throughput and scalable FFT

“…Take a 32-point FFT for example, there are 5 stages and 4 BU modules. In Stage 2, the 16 coefficient addresses for module 1 through module 4 are (0,0,0,0), (0,0,0,0), (8,8,8,8), (8,8,8,8), which increase with a stride of 8 for every 8 steps. In general, the address in Stage j starts from 0 and increases with a stride of P/2 j for every P/2 j steps.…”

“…On the other hand, the programmable DSP can not meet the system throughput requirement with an efficient energy cost. Application-specific instruction set processor (ASIP) has emerged in recent decades as an intermediate design option between ASIC and general purpose DSP, which extends some base processor core with applicationspecific custom hardware for computation acceleration [7], [8]. Hence, it can offer both good flexibility with base core software control and high throughput with hardware acceleration, providing a feasible design choice for highthroughput and scalable FFT algorithms.…”

Amdahl’s Law Revisited for Single Chip Systems

“…In Ref. 20 an application specific DSP (ASDSP) is discussed and tuned to perform FFT operations. It excels when compared with two general DSPs (30% average improvement).…”