Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

Brox, Piedad; Martínez-Rodríguez, Macarena C.; Tena-Sánchez, Erica; Baturone, I.; Acosta, Antonio

doi:10.1002/cta.2058

Cited by 5 publications

(3 citation statements)

References 39 publications

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“…It paves the way for the application of MPC technology in high-speed systems and resource-constrained applications. Compared with other schemes described in the literature, the LB-NMPC control strategy proposed by Brox et al 140 saves up to 86% in power consumption. On the other hand, leakage power is becoming more and more important in the new generation of integrated circuit chips.…”

Section: Integrated Circuitmentioning

confidence: 98%

Emerging methodologies in stability and optimization problems of learning‐based nonlinear model predictive control: A survey

Meng

Shen

Karimi

2022

Circuit Theory & Apps

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Since last 40 years, the theory and technology of model predictive control (MPC) have been developed rapidly. However, nonlinear MPC still faces difficulties such as high online computational complexity and inability to accurately model the system. In order to improve or solve the problems mentioned above of MPC, recent researches have deepened the learning‐based control. The learned method can model unknown or highly uncertain nonlinearities. And the emergence of efficient algorithms has greatly improved the feasibility of computing. Stability is at the heart of control design. Learning‐based nonlinear model predictive control (LB‐NMPC) has achieved systematic research results in the past 10 years. But the stability of LB‐NMPC is still an open question that has not been fully addressed in the literature. This review mainly summarizes the latest research progress of LB‐NMPC. More specifically, the uncertainty and online optimization problems of the considered systems are investigated mainly focusing on the use of learning techniques. At the same time, the research hotspots such as the control stability and constraint satisfaction of LB‐NMPC are briefly discussed. Finally, the application of LB‐NMPC technology in integrated circuits, path tracking control, and other fields is reviewed, which provides a reference for the research and application of LB‐NMPC.

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Section: Integrated Circuitmentioning

confidence: 98%

Emerging methodologies in stability and optimization problems of learning‐based nonlinear model predictive control: A survey

Meng

Shen

Karimi

2022

Circuit Theory & Apps

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“…The architecture of this unit, based on the one exposed in [ 30 ], is composed of the SRAM, the Address Generator, and the Arithmetic blocks.…”

Section: Architectural Description Of the Sensormentioning

confidence: 99%

VLSI Design of Trusted Virtual Sensors

Martínez-Rodríguez

Prada-Delgado

Brox

et al. 2018

Sensors

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This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μs. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

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“…The SRAM IP module was included in two different digital ASICs (hereafter referred to as ASICa and ASICb). The ASICs implement different signal processing algorithms, so their layouts are different (ASICa and ASICb are described in [30] and [31], respectively). In both cases, the SRAM module was used to store a set of parameters that the ASICs need for digital signal processing.…”

Section: B Evaluation Strategymentioning

confidence: 99%

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

Baturone

Prada-Delgado

Eiroa³

2015

IEEE Trans.Inform.Forensic Secur.

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Abstract-This paper presents a method to simultaneously improve the quality of the identifiers, secret keys, and random numbers that can be generated from the start-up values of standard Static Random Access Memories, SRAMs. The method is based on classifying memory cells after evaluating their startup values at multiple measurements in a registration phase. The registration can be done without unplugging the device from its application context, and with no need for a complex laboratory setup. The method has been validated experimentally with standard low-power SRAM modules in two different Application Specific Integrated Circuits, ASICs, fabricated with 90-nm TSMC technology. The results show that with a simple registration the length of the identifiers can be reduced by 45%, worst-case bit error probability (which defines the complexity of the error correcting code needed to recover a secret key) can be reduced by 64%, and the worst-case minimum entropy value is improved, thus reducing the number of bits that have to be processed to obtain full entropy by 81%. The method can be applied to standard digital designs by controlling the external power supply to the SRAM using software or by incorporating simple circuitry in the design. In the latter case, a module for implementing the method in an ASIC designed in 90-nm TSMC technology occupies an active area of 42,025 μm 2 .

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Application specific integrated circuit solution for multi‐input multi‐output piecewise‐affine functions

Cited by 5 publications

References 39 publications

Emerging methodologies in stability and optimization problems of learning‐based nonlinear model predictive control: A survey

Emerging methodologies in stability and optimization problems of learning‐based nonlinear model predictive control: A survey

VLSI Design of Trusted Virtual Sensors

Improved Generation of Identifiers, Secret Keys, and Random Numbers From SRAMs

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