Application-Transparent Near-Memory Processing Architecture with Memory Channel Network

Alian, Mohammad; Min, Seung Won; Asghari-Moghaddam, Hadi; Dhar, Ashutosh Sutra; Wang, Dong Kai; Roewer, Thomas; McPadden, Adam; O'Halloran, Oliver; Chen, Deming; Xiong, Jinjun; Kim, Daehoon; Hwu, Wen-mei W.; Kim, Nam Sung

doi:10.1109/micro.2018.00070

Cited by 53 publications

(25 citation statements)

References 40 publications

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“…Recently, several proposals take advantage of 3D integration technologies to insert a custom logic in a layer of DRAM devices. In both 2D and 3D scenarios, we could observe full-core integration proposals [26,25,27,28,29,37,48,51,66,76,81,82,89]. A different approach is to move only the functional units neardata.…”

Section: Near Data Taxonomymentioning

confidence: 99%

“…Near-Memory Accelerator (NMA): Accelerators are placed outside the memory devices in a different silicon die, either by placing logic next to the device using an interposer or off-chip interconnections [52,54,72,76,77,78,79,80,81,89,102,103,104]. Nevertheless, some proposals may also propose to add logic inside the memory controller inside the processor.…”

Section: Near Data Taxonomymentioning

confidence: 99%

“…In case of typical 2D DDR DRAM-based modules, NDP designers have placed either entire cores alongside memory devices [81,82], or placed customized logic units to exploit large vector accesses [7,67,72], or explored the internal analog mechanisms by changing the memory access pattern [34,62,73,83,84,85,97].…”

Section: B Memory Architectures and Ndpmentioning

confidence: 99%

“…Mondrian [79,80] implements an algorithm-hardware co-design using the 3Dstacked memory for NDP of data analytics operators, which also apply to the data partitioning and shuffling phase of MapReduce. On the other hand, the Memory Channel Network (MCN) [81] presents another perspective of NDP on a cluster of servers. A MCN processor is integrated with a buffer device on a memory to compute MR frameworks Hadoop and Spark.…”

Section: Introductionmentioning

confidence: 99%

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Survey on Near-Data Processing: Applications and Architectures

Santos

Moreira

Cordeiro

et al. 2021

JICS

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One of the main challenges for modern processors is the data transfer between processor and memory. Such data movement implies high latency and high energy consumption. In this context, Near-Data Processing (NDP) proposals have started to gain acceptance as an accelerator device. Such proposals alleviate the memory bottleneck by moving instructions to data whereabouts. The first proposals date back to the 1990s, but it was only in the 2010s that we could observe an increase in papers addressing NDP. It occurred together with the appearance of 3D-stacked chips with logic and memory stacked layers. This survey presents a brief history of these accelerators, focusing on the applications domains migrated to near-data and the proposed architectures. We also introduce a new taxonomy to classify such architectural proposals according to their data distance.

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Section: Near Data Taxonomymentioning

confidence: 99%

Section: Near Data Taxonomymentioning

confidence: 99%

Section: B Memory Architectures and Ndpmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Survey on Near-Data Processing: Applications and Architectures

Santos

Moreira

Cordeiro

et al. 2021

JICS

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“…MCN (2018) Alian et al [54] use a lightweight processor similar to Qualcomm Snapdragon 835 as a near-memory processing unit in the buffered DRAM DIMM. The memory channel network (MCN) processor runs a lightweight OS with network software layers essential for running a distributed computing framework.…”

Section: Classification and Evaluationmentioning

confidence: 99%

Near-memory computing: Past, present, and future

Singh

Chelini

Corda

et al. 2019

Microprocessors and Microsystems

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The conventional approach of moving data to the CPU for computation has become a significant performance bottleneck for emerging scale-out data-intensive applications due to their limited data reuse. At the same time, the advancement in 3D integration technologies has made the decade-old concept of coupling compute units close to the memory -called nearmemory computing (NMC) -more viable. Processing right at the "home" of data can significantly diminish the data movement problem of data-intensive applications.In this paper, we survey the prior art on NMC across various dimensions (architecture, applications, tools, etc.) and identify the key challenges and open issues with future research directions. We also provide a glimpse of our approach to near-memory computing that includes i) NMC specific microarchitecture independent application characterization ii) a compiler framework to offload the NMC kernels on our target NMC platform and iii) an analytical model to evaluate the potential of NMC.

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Emerging Hardware Technologies for IoT Data Processing

Bojnordi

Behnam

2020

Intelligent Internet of Things

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Application-Transparent Near-Memory Processing Architecture with Memory Channel Network

Cited by 53 publications

References 40 publications

Survey on Near-Data Processing: Applications and Architectures

Survey on Near-Data Processing: Applications and Architectures

Near-memory computing: Past, present, and future

Emerging Hardware Technologies for IoT Data Processing

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