Applications of Vedic multiplier - A Review

Khubnani, Rashi; Sharma, Tarunika; Subramanyam, Chitirala

doi:10.1088/1742-6596/2225/1/012003

Cited by 7 publications

(2 citation statements)

References 11 publications

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“…Vedic multiplier design using basic adders, half adders, and full adders offered the longest path delay as well as more space (6) . Carry save adder, ripple carry adder, and carry skip adder are utilized for FPGA-based multiplier implementation (7) . These adders slow down the multiplication operation when the width of the inputs increases.…”

Section: Introductionmentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

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Objectives: This work objective is to construct an FPGA-based 16x16 Vedic multiplier and assess the performance of the multiplier using three distinct architectures: pipeline, wave pipeline, and modified wave pipeline in terms of delay and clock skew. Methods: The 16 × 16 Vedic multiplier was constructed and designed through four numbers of an 8x8 Vedic multiplier. For the 16x16 Vedic multiplier, the 3-stage pipeline and wave pipeline techniques are applied, and the delay performances of the Vedic multiplier are compared. Delay optimization: In the wave pipeline Vedic multiplier architecture, the delay is decreased by inserting the known delay on the longest path delay between the multiplier and adder. Clock skew optimization: The clock skew issue of the wave pipeline Vedic multiplier architecture is minimized by adjusting the setup time violation of the clock signal that is connected to the input and output registers. Findings: The delay performance of the Vedic multiplier was evaluated by the synthesis tools Xilinx 12.1, Xilinx ISE 14.2, and Altera, and based on the synthesis report, the Xilinx synthesis tool offers 73.71% delay performance for the pipeline approach and 53.39% for the wave pipeline approach compared to the Altera tool. Further delay is reduced by the proposed modified wave pipeline approach, which saves 2.122 ns of delay compared to the wave pipeline architecture. The clock skew performance was analyzed using the Time Quest timing analyzer tool, and it was minimized to 0.035 from 0.048 compared to the wave pipeline approach. Novelty: In this work, the modified wave pipeline approach has been applied to the existing Vedic multiplier architecture, and it offers less delay as well as less clock skew compared to the existing method. Hence, the performance of the Vedic multiplier with a modified wave pipelined approach was evaluated through a 3-tap FIR filter by applying a vibroarthrography signal. Keywords: Pipeline, Wave Pipeline, Vedic Multiplier, Clock skew, Set up violation, Altera quartex- II Time quest timing analyzer tool

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Section: Introductionmentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

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“…The Half Adder (HA) and Full Adder (FA) is the primary building components of adder architectures (FA). To sum up long bit lengths, the RCA design uses oating FA units in sequence, however, this adder suffers from a signi cant latency [Khubnani(2022)]. Using Vedic methods to address issues, demands a higher degree of mental calculation which necessitates mind arithmetic.In this paper, we need to come up with a new mathematical architecture using Urdhva-Tiryagbhyam and Nikhilam navatascaramam sutra to give a solution easily.With the assistance of a DSP changing the settings is a straightforward procedure that involves ashing a code or programming a DSP.…”

Section: Introductionmentioning

confidence: 99%

Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

RAMAMOORTHY,

PERIASAMY

2023

Preprint

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Digital signal processing (DSP) is a vast and active field of research. High throughput is required for most wireless communication systems. The Fast Fourier Transform (FFT), which lies at the heart of most modulators, is a major stumbling block to communication.The intrinsic floating-point multiplier units located within the butterfly units of every FFT execute these calculations. The performance of FFT in terms of throughput is limited by multiplication. As a result, Multiplier topologies with reduced truncation errors are needed for high-speed, low-power systems. This paper presents high-performance FFT units for DSP processor cores based on hybrid Vedic multiplier units. The Vedic multiplier that has been presented is based on the Vedic multiplication sutras. In the decimal number system, these sutras have historically been employed to multiply two numbers. In this study, a hybrid Vedic multiplier based on Indian Vedic mathematics' Urdhva-Tiryagbhyam and Nikhilam navatascaramam sutra is suggested. An efficient multiplier is the fundamental goal of this study, which aims to minimize the size and delay path of a multiplier while enhancing the performance of the processor. Verilog HDL was used to implement the complete design. Xilinx ISE Design Suite 14.5, which is used for synthesis and simulations, was used. It is matched to previously reported Vedic multiplier designs in terms of speed and area consumed. It features a speedier development process and a lower computation complexity than the traditional multiplier.

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Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

Karthi Kumar,

Vimal

2024

Measurement: Sensors

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Applications of Vedic multiplier - A Review

Cited by 7 publications

References 11 publications

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Design of a Novel Arithmetic Architecture Using Hybrid Vedic Sutras in Digital Signal Processing Applications

Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

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