Applying Supervised Learning to the Static Prediction of Locality-Pattern Complexity in Scientific Code

Alsaedi, Nasser; Carr, Steve; Fong, A.C.M.

doi:10.1109/icmla.2018.00162

Cited by 1 publication

(1 citation statement)

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“…Our aim through this paper is to propose a method to build cache-miss models that exhibits a higher correlation between the source-code performance and the host-hardware characteristics. To the best of our knowledge, the closest data-cache-miss modeling methods similar to our work are proposed in [19] and [1]. These methods estimate the data-cache-miss model of a program by analyzing its corresponding data-reuse distance (defined as the number of distinct data elements accessed between two consecutive reference to the same element [19]).…”

Section: Algorithm Sourcementioning

confidence: 99%

Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization

Lakhdar

Charles

Kooli

2019

Proceedings of the 30th International Workshop on Rapid System Prototyping (RSP'19)

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Adapting a source code to the specificity of its host hardware represents one way to implement software optimization. This allows to benefit from processors that are primarily designed to improve system performance. To reach such a software/hardware fitting without narrowing the scope of the optimization to few executions, one needs to have at his disposal relevant performance models of the considered hardware. This paper proposes a new method to optimize software kernels by considering their data-access mode. The proposed method permits to build a data-cache-miss model of a given application regarding its specific memory-access pattern. We apply our method in order to evaluate some custom implementations of matrix data layouts. To validate the functional correctness of the generated models, we propose a reference algorithm that simulates a kernel's exploration of its data. Experimental results show that the proposed data alignment permits to reduce the number of cache misses by a factor up to 50%, and to decrease the execution time by up to 30%. Finally, we show the necessity to integrate the impact of the Translation Lookaside Buffers (TLB) and the memory prefetcher within our performance models.

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Section: Algorithm Sourcementioning

confidence: 99%