Applying x-ray microscopy and finite element modeling to identify the mechanism of stress-assisted void growth in through-silicon vias

Abstract

Fabricating through-silicon vias (TSVs) is challenging, especially for conformally filled TSVs, often hampered by the seam line and void inside the TSVs. Stress-assisted void growth in TSVs has been studied by finite element stress modeling and x-ray computed tomography (XCT). Because x-ray imaging does not require TSVs to be physically cross-sectioned, the same TSV can be imaged before and after annealing. Using 8 keV laboratory-based XCT, voids formed during copper electroplating are observed in as-deposited samples and void growth is observed at the void location after annealing. We hypothesize that the mechanism generating voids is hydrostatic stress-assisted void growth. Stresses in a copper-filled TSV with a pre-existing void were simulated by finite element methods. The peaks of the hydrostatic stress and its gradient are shown to be around the edge of the void. Comparing simulated results and experimental data shows that void growth in TSVs is stress-assisted: v acancies diffuse and coalesce at the void as a result of the hydrostatic stress gradient

The Impact of Organic Additives on Copper Trench Microstructure

“…However, it is hypothesized that there is a competition between the increased lattice strain caused by the impurities 34 and the stress relief from void formation. 35 Once a critical void area is observed in the Cu (~2000 nm 2 per trench in this study), there is a major reduction in stress.…”

Experimental measurement of the effect of copper through-silicon via diameter on stress buildup using synchrotron-based X-ray source

“…Additionally, our earlier study [25] and that of Kong et al [32] show that void formation and growth in Cu TSVs increase with the peak cycling/annealing temperature. Studies reported by Shaw et al [33] show that void density in Cu dramatically increases for annealing temperatures above 400°C.…”

Investigation of silicon stress around through silicon vias by high efficiency micro-Raman microscopy

“…For silicon, the Raman penetration depth ranges up to 2 μm, again depending on the laser wavelength. Moreover, the Raman technique can be used to measure the near-surface stresses in Si around TSVs even with an oxide layer covering the wafer surface because the laser can penetrate the oxide layer with nearly 95% transparency [4][5][6][7][8][9][10][11][12][13][14][15]. In this paper, we reports our recent progress on the stress measurement by high efficiency micro-Raman microscopy.…”