Approach to analyze decomposition impact for photomask fabrication

Toyama, Nobuhito; Adachi, Takashi; Inazuki, Yuichi; Sutou, Takanori; Nagai, Tomoaki; Morikawa, Yasutaka; Mohri, Hiroshi; Hayashi, Naoya

doi:10.1117/12.729022

Cited by 3 publications

(4 citation statements)

References 2 publications

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“…Thus it considerably impact the time of OPC process followed. Natural split and cutting are both feasible methods to implement splitting for above pattern as showed in Figure 3 [2]. By complying some design constraints and/or rules, we may choose rough decomposition ways.…”

Section: Re-cuts Related Decomposition (Rrd)mentioning

confidence: 99%

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A new OPC method for double patterning technology

Pan

Chen

2008

Optical Microlithography XXI

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As the VLSI technology scales into deep submicron nodes, Double Patterning Technology (DPT) has shown its necessity for the under 45nm processes. However, the litho-related and process-related issues, such as the overlay control for CD uniformity, decomposition, feature stitching technology and some other problems make up the main challenges for the implementation of DPT. Due to Optical Proximity Correction (OPC), the complexity and data volume of DPT increase dramatically, which severely increase the application cost and create manufacturability problems.In this paper, we mainly talk about the interactions between DPT and OPC and propose a new Model-Based OPC methods for the decomposition in DPT procedures. To address the printing problems with cutting sites for feature split, we introduce an overlap correction method on the stitching locations. For any re-cut and/or redesigned pattern after verification, we categorize DP decompositions and introduce a new Adaptable OPC (Ad-OPC) algorithm by reusing post OPC layout to speed up the correction and improve its convergence according to environment surrounding. The method can be easily incorporated into existing MB-OPC framework. To test this method, total Edge Placement Error (EPE) and runtime are calculated in our experiments. Results show that over 90% runtime can be saved compared with conventional OPC procedure. It increases the robustness and friendliness of pattern correction as well as stitches features back satisfactorily.

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Section: Re-cuts Related Decomposition (Rrd)mentioning

confidence: 99%

“…As one of the main concerns, overlay impact wafer CD directly [2]. However, constrained by current lithography tool, it may be difficult to eliminate overlay error but reach certain optimized overlay accuracy.…”

Section: Introductionmentioning

confidence: 99%

A new OPC method for double patterning technology

Pan

Chen

2008

Optical Microlithography XXI

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“…Since the double patterning process includes the hard mask fabrication and dry etching process, the infrastructure requires etching and deposition equipment in order to proceed with the full double patterning process. [19][20][21][22] While a conventional single-exposure process can be evaluated using only a lithography module, double patterning has to be prepared using these expensive tools for process evaluation. There is uncertainty concerning resolution estimation with the simulation because there will be influences by unconventional aspects such as polygoncutting, split-error or split-conflict during data decomposition.…”

Section: Introductionmentioning

confidence: 99%

Double Patterning Analysis Method by Emulation Using a Double-Exposure Technique

Miyazaki

Toyama

Kawai

2010

Jpn. J. Appl. Phys.

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Double patterning lithography was utilized to break the resolution limit of lithography and is the most promising technology that enables shrinking of this limit. There are some barriers concerning evaluation of the double patterning process because it includes the hard mask fabrication and dry etching process. We proposed a new evaluation method for double patterning to analyze photomask performance with an easy and simple procedure using a double-exposure technique. Results showed this emulation method was useful in determining the impact of mask overlay and critical dimension (CD) error on double patterning lithography. We also evaluated the impact of mask overlay and CD. Both the overlay and CD difference were very good between the two masks. Correlations between mask and wafer cannot be detected because of the measured overlay error and the CD performance of masks was too small.

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“…DP technology such as side-wall-process is promising candidate in the memory industry, on the other hand the adoption of DP technology such as pitch doubling into random logic LSI have some issues such as a tight overlay control and a way of dividing pattern. Therefore, it is reported that it is difficult to adopt DP technology into the layout of random logic LSI for 32-nm [6]. This opinion is mainstream in the industry, but for the upcoming 32-nm node we lithographers should clarify the possibility of DP technology from another point of view.…”

mentioning

confidence: 96%

Study of ELS technology for random logic LSI toward 32-nm node

Setta

Morishita

Kobayashi

et al. 2008

Optical Microlithography XXI

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There has been an ongoing request to make semiconductor devices smaller and smaller. The cellblock size of SRAM is predominated by both a gate-to-contact space and a poly-to-poly space. The gate-to-contact space is defined by the leakage value from the poly electrode. So we focused on the poly-to-poly space for all shrinkage.We have been studying connected line splitting techniques. We named it ELS (end of line splitting) technology. A critical issue is to control gaps between two narrow gate-poly's line-ends or between a narrow gatepoly's line-end and a neighboring wire-poly line due to lower contrast in low-k1 lithography. In the case of standard cells, especially, the patterning of narrow gate-poly projected to wire-poly is easy to shorten. To prevent this electrical short, designers avoid keeping a narrow gap and small chip size. In order to realize a narrower gap, a splitting technique, well-known and adopted in poly's line-ends of SRAM that are regularly arrayed, is effective. We are investigating how to extend this technique as ELS technology for random logic of poly toward creating a 32-nm node.In this paper, the authors focus on the following topics: 1) data preparation technique, and 2) experimental results. Then this technology for the poly layer of random logic LSI devices is compared with result of conventional single exposure and double pattering technology. In addition, the result that overlay control issue for ELS technology is not severe compared with pitch doubling technology is described. ELS technology can help the designer and our lithographer to reduce the gap and reduce the array grid size of standard cells.Keywords: End of line, double pattering, low-k1 lithography, SRAM INTRODUCTONThe demand for making LSI's smaller has been growing every year; the ITRS roadmap of lithographic technology says that it is expected to achieve a patterning of HP (half pitch) 45-nm for gate-poly pitch at 32-nm node logic LSI. But unfortunately the lithographic infrastructure that supports this doesn't meet our schedule. To reduce the pitch resolution, a well-known Rayleigh's criterion has three important parameters. One is the k1-factor that means process difficulty, the second is the wavelength of the light source, and the third is the NA (numerical aperture) of projection lens. These three parameters compose the equation of HP = k1*(wavelength /NA). One industry expects EUV (extreme ultra-violet) lithography will be able to lower the wavelength of exposure light, another industry expects higher index immersion lithography will be able to increase the NA of the exposure lens. In the case of ArF immersion lithography, certainly, the requirement of 1.38-NA toward 32-nm node for logic LSI is discussed in ITRS 2007. Recently, the fact that these two candidates have been failing meets the requirements for the mass production in 2009-2011 has been reported [1,2]. Therefore, the lithographer should have not only managed to raise the practical k1-factor, but also lithographers should consider achieving a low-k1 litho...

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Approach to analyze decomposition impact for photomask fabrication

Cited by 3 publications

References 2 publications

A new OPC method for double patterning technology

A new OPC method for double patterning technology

Double Patterning Analysis Method by Emulation Using a Double-Exposure Technique

Study of ELS technology for random logic LSI toward 32-nm node

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