Approach to synthesis of fault tolerant reduced device count multilevel inverters (FT RDC MLIs)

Abstract

Multilevel inverters (MLIs) are rapidly acquiring techno-economic feasibility for both high-power and medium-power applications. Increased number of power switches has been cited as one of the most important limitations of MLIs; and to overcome it, a whole new class of MLI topologies has come up. These topologies are commonly called 'reduced device count' MLIs (RDC-MLIs). As the number of controlled switches is significantly reduced in RDC-MLIs, the redundant states are also reduced. Hence, the possibility of fault tolerant operation is severely affected. This study looks at the possibility of imparting fault-tolerant characteristics to RDC-MLIs. In this study, some of the recently proposed RDC-MLI topologies are first analysed for the possibility of fault tolerant operation in the case of 'any single switch open-circuit fault (ASSOF)'. Thereafter, an optimal addition of power switch is proposed which enables fault tolerant operation in the event of ASSOF. Furthermore, these modified RDC-MLIs are verified under normal and faulty conditions using software simulations and experimental setups and these results are presented.

Resilient multilevel inverter topology with improved reliability

“…The topologies proposed in [15–33] utilise redundant leg and external switches/relays to make the topology as fault tolerant. The main drawback of those topologies is that external switches or redundant leg have zero percentage utilisation under healthy operation.…”

“…However, the power loss of the system is increased due to the utilisation of redundant leg switches under healthy operation. Similarly, a five‐level fault‐tolerant inverter topology is proposed with a redundant switch in [31]. The added redundant switch is unutilised under healthy operation is the limitation of the topology.…”

Single‐phase boost DC‐link integrated cascaded multilevel inverter for PV applications

“…8a and 9a that for a particular power rating, the inductor size decreases with an increase in the switching frequency. From (10), (15) and (16), the minimum capacitances C 1 min and C 2 min of C 1 and C 2 required to limit ripple voltage to ΔV c1 and ΔV c2 , respectively, are given as follows:…”

“…Thus, it leads to increased cost and reduced efficiency. A few MLI topologies are reported with reduced switch count and voltage sources [6][7][8][9][10][11] to improve compactness and efficiency. New pulse-width modulation (PWM) techniques [9] are presented to maintain constant CMV and reduce leakage currents in cascaded half-bridge MLI topologies.…”

“…New pulse-width modulation (PWM) techniques [9] are presented to maintain constant CMV and reduce leakage currents in cascaded half-bridge MLI topologies. Also, fault-tolerant methods [10] are incorporated for reduced switch count SCMLI (RSCMLI). However, none of these topologies offers high gain boost factor, which is essential in renewable energy applications.…”