Approximate Adder with Hybrid Prediction and Error Compensation Technique

Yang, Xinghua; Xing, Yue; Qiao, Fei; Wei, Qi; Yang, Huazhong

doi:10.1109/isvlsi.2016.16

Cited by 8 publications

(9 citation statements)

References 7 publications

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“…Hence, ETAII is likely to cause a high magnitude error. Confirming this, Yang et al [27] noted that ETAII resulted in almost a corrupted image when considered for digital image processing. Further, based on a FPGA implementation, we found that ETAII consumes more resources and is slower than the (native) accurate FPGA adder.…”

Section: Survey Of Static Approximation Adders Suitable For Asic mentioning

confidence: 75%

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

et al. 2021

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Section: Survey Of Static Approximation Adders Suitable For Asic mentioning

confidence: 75%

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

et al. 2021

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“…For a given k, accuracy further depends on l. Therefore, one possible way to improve accuracy without affecting delay benefits is to increase l. However, as l increases, the required number of sub-adders increases, which imposes power and area overheads. Based on the relationship between k and l, several ESAs have been proposed in the literature [15][16][17][18][19][20][21][22][23][24][25]. In case of ESAs proposed in [15-21, 23, 25], k needs to be fixed a priori.…”

Section: Background Of Esasmentioning

confidence: 99%

“…Two commonly used approaches to limit the length of carry propagation are: (i) Approximate Full Adder (AFA) [10][11][12][13][14]; and (ii) Equal Segment Adder (ESA) [15][16][17][18][19][20][21][22][23][24][25]. In the first approach (see Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Further, for a given value of k , l is also fixed in these ESAs ( l = 0 in [18],

l = k / 2

in [17, 20, 21, 23, 25] and

l = k - 1

in [15, 16]). Consequently, the design flexibility of ESAs proposed in [15–21, 23, 25] is limited. On the other hand, ESAs proposed in [22, 24] provide a high degree of design flexibility by updating k and l dynamically.…”

Section: Introductionmentioning

confidence: 99%

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Accuracy enhancement of equal segment based approximate adders

Dutt

Nandi

Trivedi

2018

IET Computers & Digital Techniques

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Recently, several approximate adders have been proposed based on the design concept of Equal Segment Adder (ESA), i.e. to segment an N-bit adder into several smaller and independent equal size sub-adders. In this study, the authors propose analytical models to estimate Pass Rate (PR), delay, power and area of ESAs, where PR represents the probability of output to be correct. From the proposed analytical models, they observe that there is a scope and need for improvement in quality-effort curves of existing ESAs. Intended to improve the quality-effort curves, they propose modifications in existing ESAs with design objective that modified ESAs provide higher accuracy without imposing any additional delay, power and area overheads. Both the authors' analytical and simulation results show that modified ESAs provide higher accuracy, better qualityeffort curves and more optimal Delay-Power-Area-Accuracy trade-off as compared to original ESAs. In addition to accuracy enhancement, the proposed approach also provides improvements in delay and power when ESAs are used with Error Detection and Correction logic. For evaluating the effectiveness of the proposed approach in real-life applications, they process Lena image using original ESAs and modified ESAs. Their image processing results show that modified ESAs provide more precise images as compared to original ESAs.

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“…In adders, the addition process is governed by the carry generation and propagation mechanism [12,13,14]. Some well-known adders designed using approximation techniques are named as speculative [15,16], segmented [17,18] and carry select adders [19,20]. However, this design approach is not suitable for energy-efficient circuits as this process requires multiple overlapping sub-adders [21].…”

Section: Introductionmentioning

confidence: 99%

High-performance approximate half and full adder cells using NAND logic gate

Waris

Wang

Liu

2019

IEICE Electron. Express

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In this letter, NAND-based approximate half adder (NHAx) and full adder (NFAx) cells are proposed for low power approximate adders. NHAx and NFAx architectures are built using NAND logic gate which has a minimal normalized gate delay among all the CMOS based integrated circuit digital logic family; therefore, an improvement of 29% in the critical path delay is achieved. For the performance evaluation, 8-bit ripple carry adder (RCA) is then built using proposed cells. RCA-NFAx shows a good power-efficiency trade-off when both power delay product and error metric NMED are considered with reference to the previous approximate 1-bit FA based RCA designs.

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Approximate Adder with Hybrid Prediction and Error Compensation Technique

Cited by 8 publications

References 7 publications

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

Accuracy enhancement of equal segment based approximate adders

High-performance approximate half and full adder cells using NAND logic gate

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