Approximate radix-8 Booth multiplier for low power and high speed applications

Boro, Bipul; Reddy, K. Manikantta; Kumar, Yogesh; Vasantha, M. H.

doi:10.1016/j.mejo.2020.104816

Cited by 24 publications

(2 citation statements)

References 29 publications

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“…All of these multiples are easily obtained by using shift and negation operations on X. Similarly, Radix-8 MBE requires X multiples of 0, 1, 2, 3, and 4, while lowering the height of the PP matrix from N to N/3 16 . The redundant binary PPG achieves the largest reduction in the number of PPs, around 75%, for a Radix-4 multiplier 17 .…”

Section: Related Workmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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A technique for efficiently multiplying two signed numbers using limited area and high speed is presented in this paper. This work uses both the Booth and Vedic multiplication sutra methodologies to enhance the speed and reduction in the area by using two VLSI architectures of radix encoding techniques—Radix-4 and Radix-8—with the Vedic multiplier. The functionality of the proposed methods is tested using an Artix-7 Field Programmable Gate Array (FPGA-XC7A100T-CSG324) in Xilinx Vivado 2019.1 and ASIC 45 nm technology. Two methods of Booth encoding using Vedic multiplier (Urdhva-Tiryakbhyam sutra) were used to develop, and examine the benefits of rapid computational multiplier. The results of the proposed multiplier for Booth-Vedic-Radix-4 encoding (BVR-4) decrease area by 89% and improve Area-Delay Product (ADP) by 72% for a 16-bit multiplier when subjected to other existing multipliers. The Booth-Vedic-Radix-8 (BVR-8) method shows that there will be an 89% reduction in area and an improvement in ADP by 72% for the 16-bit multiplier. The performance is evaluated regarding area occupancy (i.e., LUTs number) and propagation delay (output time). In terms of resource utilization, the proposed BVR-4 and BVR-8 multipliers outperform all the current designs with a marginal effect on speed and area for narrower bit-width ranges.

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Section: Related Workmentioning

confidence: 99%

A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications

Kalaiselvi,

Sabeenian

2023

Sci Rep

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“…M ULTIPLICATION is one of the most widely used arithmetic operations in a variety of applications, such as machine learning [1]- [7], image/video processing [8]- [12], and cryptographic operations [12]- [16]. Multipliers often cause computational bottlenecks, so that optimizing their efficiency is crucial [11], [17]- [19]. Embedded systems and high-performance computing devices incorporate a diverse range of multipliers, which vary in terms of their bit-length, internal architecture, and operational principles.…”

Section: Introductionmentioning

confidence: 99%

Programmable All-in-One 4×8-/2×16-/1×32-Bits Dual Mode Logic Multiplier in 16 nm FinFET With Semi-Automatic Flow

Shavit,

Stanger,

Taco

et al. 2023

IEEE Access

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In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting single-instruction-multiple-data (SIMD)-like systems is proposed. The design introduces improvements at both the architecture and logic gate levels, by capitalizing on their synergistic combination. At the architecture level, the multiplier design is adapted to accommodate diverse computations based on the level of the input data parallelism. The main novelty is the incorporation of three different acceleration or bypass mechanisms jointly. The configurable multiplier has three variable precision configuration options: a 32x32-bit, two 16x16-bit, and four 8x8-bit multipliers. This bypassing architecture seamlessly integrates DML logic, which supports two modes of operation: a high-performance dynamic mode and a low-energy consumption static mode, with smooth mode switching capabilities. By optimizing the DML mode based on the multiplier's bit-width, the design enhances active computational block utilization, overall performance, and energy efficiency. In the dynamic mode, the DML implementation achieves an average performance improvement of 15% for the 32-bit, 8% for the 16-bit, and 7% for the 8-bit multipliers compared to the CMOS implementation. In the static mode, the DML implementation demonstrates an average energy reduction of 28%. When running in combined mode, where the 32-bit multiplier operates in dynamic mode for acceleration and the 8-bit multiplier operates in static mode for energy savings, the DML implementation exhibits an average overall performance gain of 15% and up to 18% lower energy consumption. The nontrivial semi-automation flow utilized for the complex implementation of the proposed architecture is also presented.

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