Approximate reachability with BDDs using overlapping projections

Govindaraju, S.; Dill, David L.; Hu, Alan J.; Horowitz, Mark

doi:10.1145/277044.277169

Cited by 31 publications

(17 citation statements)

References 9 publications

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“…In contrast to the approaches in [8,12,11,47,53], we allow for overlapping subsets of the variables. Our research [29,30,31,32,34] shows that overlapping projections are a more refined approximation scheme compared to earlier schemes based on disjoint partitions.…”

Section: Related Workmentioning

confidence: 74%

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Approximate Symbolic Model Checking Using Overlapping Projections

Govindaraju¹,

Dill²

1999

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Section: Related Workmentioning

confidence: 74%

“…Clarke et al [16] explored this same basic idea in verification using abstraction functions for different variables in a SMV program. We explore the same basic idea in the context of approximation by overlapping projections [29]. …”

Section: Initial Approximationmentioning

confidence: 99%

Approximate Symbolic Model Checking Using Overlapping Projections

Govindaraju¹,

Dill²

1999

Self Cite

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“…Obtaining don't care states can be done in several ways; while many DCS are inherently known to the designers, others can be found through reachability analysis [8] and through efficient approximation methods using Binary Decision Diagrams (BDD) [5] [11] [13].…”

Section: Introductionmentioning

confidence: 99%

“…First, DCS are found and extracted using existing BDD techniques [5]. Second, using our developed heuristics, non beneficial DCS are identified and discarded.…”

Section: Introductionmentioning

confidence: 99%

Utilizing don't care states in SAT-based bounded sequential problems

Safarpour

Fey

Veneris

et al. 2005

Proceedings of the 15th ACM Great Lakes Symposium on VLSI

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Boolean Satisfiability (SAT) solvers are popular engines used throughout the verification world. Bounded sequential problems such as bounded model checking and bounded sequential equivalence checking rely on fast and robust SAT solvers. In this work, we introduce a technique that improves the performance of the underlying SAT solver for bounded sequential problems by taking advantage of a design's don't care states. We develop cost effective methods of filtering, replicating and applying the don't care states to the original problem thus reducing the search space. Experiments demonstrate the effectiveness of the proposed method on ISCAS'89 benchmarks.

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“…There is much room left for improving the accuracy of the approximations. Approximations from different algorithms can be intersected to produce tighter upper bounds, techniques like those of Warwukiewicz (Berkeley 1994 unpublished) and Govindaraju et al [9] show that overlapping subystems in the state space decomposition can be advantageous.…”

Section: Discussionmentioning

confidence: 99%

Approximate Reachability Don't Cares for CTL model checking

Moon¹,

Jang²,

Hachtel³

et al.

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

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RDCs (Reachability Don't Cares) can have a dramatic impact on the cost of CTL model checking [18]. Unfortunately, RDCs, being a global property, are often much more difficult to compute than the satisfying set of typical CTL formulas. We address this problem through the use of Approximate Reachability Don't Cares (ARDCs), computed with the algorithms developed for the VERITAS sequential synthesis package [4,5]. Approximate Reachable states represent an upper bound on the set of true reachable states, and thus a lower bound on the set of unreachable (Don't Care) states. ARDCs can be 10X to 100X (or much more for very large circuits) cheaper to compute than RDCs, and in some cases have the same dramatic effect on CTL model checking as the real RDCs. We also discuss the application of ARDCs to the problem of exact computation of the RDCs themselves. Experiments on industrial benchmarks show that order of magnitude speedups are possible, and occur frequently. The experimental results presented strongly support our claim that ARDCs play a safe and important way out of a serious dilemma: RDCs are necessary for tractable model checking of many large circuits, but the computation of the RDCs themselves is often intractable. We include, and theoretically justify, significant extensions of the VERITAS algorithms, and show that they can be up to an order of magnitude faster, while computing a virtually identical upper bound.

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Approximate reachability with BDDs using overlapping projections

Cited by 31 publications

References 9 publications

Approximate Symbolic Model Checking Using Overlapping Projections

Approximate Symbolic Model Checking Using Overlapping Projections

Utilizing don't care states in SAT-based bounded sequential problems

Approximate Reachability Don't Cares for CTL model checking

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