Approximate XOR/XNOR-based adders for inexact computing

Abstract

Power dissipation has become a significant issue for integrated circuit design in nanometric CMOS technology. To reduce power consumption, approximate implementations of a circuit have been considered as a potential solution for applications in which strict exactness is not required. In inexact computing, power reduction is achieved through the relaxation of the often demanding requirement of accuracy. In this paper, new approximate adders are proposed for low-power imprecise applications. These adders are based on XOR/XNOR gates with multiplexers implemented by pass transistors. The proposed approximate XOR/XNOR-based adders (AXAs) are evaluated and compared with respect to energy consumption, delay, area and power delay product (PDP) with an accurate full adder. The metric of error distance is used to evaluate the reliability of the approximate designs. Simulation by Cadence's Spectre in TSMC 65nm process has shown that the proposed designs consume less power and have better performance (such as a lower propagation delay) compared to the accurate XOR/XNOR-based adder, while the error distance remains similar or better than other approximate adder designs.

Design and Implementation of Low Power Inexact Floating Point Adder

“…An inexact fixed-point adder has been extensively studied and can be used in the exponent adder inexact adders such as lower-part-OR adders (LOA) [3], approximate mirror adders [4], approximate XOR/XNORbased adders, and equal segmentation adders [6], [7] can be found in the literature [1,2,3]. For a fast FP adder, a revised LOA adder is used, because it significantly reduces the critical path by ignoring the lower carry bits.…”

“…The m-bit adder is used for the m most significant bits of the sum, while then-bit adder consists of OR gates to compute the addition of the least significant n bits (i.e. the lower n-bit adder is an array of n two-input OR gates) [6]. In the original LOA design, an additional AND gate is used for generating the most significant carry bit of then-bit adder; in this work, all carry bits in then-bit inexact adder are ignored to further reduce the critical path.…”

“…Inexact chips are smaller, faster and consume less energy. For inexact computing, fixed point arithmetic circuits have been already studied [2], [3], [4], [5], [6], [7], [8] as mentioned in the literature floating-point (FP) circuits consumes significantly more power due to its more complexity they have not been recommended for inexact computing. In computationally intensive applications FP format offers a large range dynamically.…”

Energy-Efficient Digital Processing via Approximate Computing

“…4.3). In [19,54] the authors propose a similar idea, but in this case they generate approximate FAs with transistor-level simplifications. These solutions directly reduce area and power (by affecting leakage, internal capacitances, and switching activity) and also decrease the delay of the FA, improving its performance, or alternatively enabling a more aggressive voltage scaling, to further reduce power consumption.…”

An Efficient Accuracy Switchable Majority Based Prefix Adder

“…There have been approximate full adders proposed such as the approximate mirror adder(AMA) designs proposed in [20] and the approximate XOR based adder (AXA1) and approximate XNOR-based adders(AXA2, AXA3) proposed in [21]. Some approximate subtractor(AXSC) designs were proposed in [22].Their design uses a correct adder-subtractor for the most significant bits and uses an approximate adder-subtractor design for the least significant bits.…”