Approximation-Aware Coordinated Power/Performance Management for Heterogeneous Multi-cores

Kanduri, Anil; Miele, Antonio; Rahmani, Amir M.; Liljeberg, Pasi; Bolchini, Cristiana; Dutt, Nikil

doi:10.1109/dac.2018.8465797

Cited by 8 publications

(13 citation statements)

References 7 publications

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“…Table 9.1 Average, standard deviation, and overall contribution to the overall latency of each actor of the object detection application in Fig. 9.6 when processing a test sequence of 9 149 images and executed each in isolation on a single core running constantly at maximum frequency according to [3,10,21,26] to enforce the global latency upper bound UB L = 115 ms for the given application. Due to the small variation and overall latency contribution of all except the actors SD and SM according to Table 9.1, we dedicate a time budget of 20 ms to the other actors altogether, assuming that their cumulative latency per input image does not exceed this budget.…”

Section: Enforcement Problem Descriptionmentioning

confidence: 99%

Run-Time Enforcement of Non-functional Program Properties on MPSoCs

Teich

Mahmoody

Pourmohseni

et al. 2020

A Journey of Embedded and Cyber-Physical Systems

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A many-core architecture is typically organized as a set of so-called storage, I/O, and compute tiles which are interconnected by a Network-on-Chip (NoC) for scalability, see, e.g., Fig. 9.1. Memory and I/O tiles enable mass storage and offchip access, respectively. Each compute tile is typically organized as a multi-core or a processor array and comprises a set of processing cores, peripherals such as memories, and a network adapter which are interconnected via one or more buses. An application to be executed on the architecture is typically composed of a set of processing tasks with known data dependencies, provided as a task graph. In case of periodic applications, actor-based models of computation and languages such as ActorX10 [17] may be used for parallel programming of MPSoCs. Each application may be augmented with one or a set of requirements on specific non-functional properties of its execution, e.g., execution time, throughput, or power corridors. In the following, a mapping of an application on a given architecture corresponds to a binding of its tasks to platform cores, a routing of the data exchanged between communicating tasks, an allocation of the required processing, communication, and storage resources, and a scheduling of tasks and communications on the allocated

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Section: Enforcement Problem Descriptionmentioning

confidence: 99%

Run-Time Enforcement of Non-functional Program Properties on MPSoCs

Teich

Mahmoody

Pourmohseni

et al. 2020

A Journey of Embedded and Cyber-Physical Systems

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“…Performance models have been developed to estimate throughput due to configuration variations only on the CPU. Throughput (th j ) of an application j (or in general its performance) running on a single cluster i (either big or LITTLE) has an almost linear relationship with the CPU quota Q j assigned to the application and cluster's frequency level f i , whereas there is a sublinear relationship with the parallelization level #t (in number of assigned CPU cores), as shown in [4], [13]. Furthermore, as in [3], it is reasonable to estimate an average performance ratio between big and LITTLE clusters at the same baseline frequency, namely r b→L .…”

Section: A Power and Performance Modelsmentioning

confidence: 99%

“…Runtime Resource Controller. We implemented a controller similar to the one proposed in [13]. It consists of a process running in user-space, capable of 1) accessing all HW sensors and knobs through Linux interface, 2) controlling process allocation by means of the cgroups mechanism, and 3) measuring applications' performance in terms of throughput with the HeartBeat mechanism.…”

Section: Introductionmentioning

confidence: 99%

A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores

Angioletti

Bertani

Bolchini

et al. 2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Nowadays, runtime workload distribution and resource tuning for heterogeneous multicores running multiple OpenCL applications is still an open quest. This paper proposes an adaptive policy capable at identifying an optimal working point for an unknown multiprogrammed OpenCL workload without using any design-time application profiling or analysis. The approach compared against a design-time optimization strategy demonstrates to be effective in converging to an solution guaranteeing required performance while minimizing power consumption and maximum temperature; it achieves on average values 0.085 W (5.15%) and 0.83 • C (1.47%) worse than the static optimal solution.

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“…This can be extended in the context of both multi-core and many-core systems running emerging workloads from media processing domains and can be exploited opportunistically subject to application requirements (El-Harouni et al, 2017;Palomino et al, 2016). Particularly with battery operated mobile processors and resource constrained systems, approximation can be used for efficient resource allocation (Kanduri et al, 2018b).…”

Section: Accuracy Bound Qos Managementmentioning

confidence: 99%

On-Chip Dynamic Resource Management

Miele

Kanduri²,

Moazzemi³

et al. 2019

FNT in Electronic Design Automation

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The need for dynamic resource management has shadowed the exponential growth of on-chip transistor capacity, and the challenge is accentuated by the heterogeneity of resources, and the bewildering variety of constraints and requirements of applications, platforms and users. The field has started with a few research papers in the early 1990s but has grown today to over hundred yearly publications, leading to an accumulated body of literature presumable far above 1000 papers. We focus on the dynamic (run-time) management of onchip resources and mostly ignore design-time techniques and off-chip resources of larger electronic systems. Moreover, we do not attempt a complete review of all published work on the topic. Rather, this survey provides a structured review and discussion of the state of the art and is divided along the primary objectives of resource management techniques: performance, power, reliability and quality of service, each

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Approximation-Aware Coordinated Power/Performance Management for Heterogeneous Multi-cores

Cited by 8 publications

References 7 publications

Run-Time Enforcement of Non-functional Program Properties on MPSoCs

Run-Time Enforcement of Non-functional Program Properties on MPSoCs

A Runtime Resource Management Policy for OpenCL Workloads on Heterogeneous Multicores

On-Chip Dynamic Resource Management

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