Approximation of the worst-case execution time using structural analysis

Abstract

We present a technique to approximate the worst-case execution time that combines structural analysis with a loop-bounding algorithm based on local induction variable analysis. Structural analysis is an attractive foundation for several reasons: it delivers better bounds on the number of executions for each basic block than previous approaches, its complexity is well understood, and it allows the compiler to easily work on Java bytecode without requiring access to the original program source. There are two major steps. We first compute (min, max) bounds on the number of iterations for each loop. Then we use precise structural information to propagate these bounds to the whole control-flow graph and compute a bound for each basic block. Such a fine-grained result eases the identification of infeasible paths and improves the approximation of the worst-case execution time of a function or method. This analysis was successfully implemented in an ahead-of-time Java bytecode to native compiler and produces input for a worst-case execution time estimator. We describe the effectiveness in reducing the worst-case execution time for a number of programs from small kernels and soft-real-time applications.

A study of irreducibility in C programs

“…In parallel, the algorithm constructs a control tree that represents the hierarchical structure of the regions within the original graph. In other work, structural analysis has been used to approximate the worst-case execution time of programs [38] and to perform thread partitioning [39].…”

TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs

“…The worst case execution time of an application and the maximum number of main memory accesses estimated using worst-case timing analysis [4,5] serve as the required CHP to select a single application specific cache memory. Even though real-time systems are usually application specific [18,9] and the maximum number of main memory accesses acceptable for the WCDMOT can be estimated using the worst-case timing analysis, inter-influencing cache memories in the multi-level data cache hierarchy do not allow required CHP to be extracted from the number of memory accesses.…”