architect: Arbitrary-precision constant-hardware iterative compute

Abstract

Many algorithms feature an iterative loop that converges to the result of interest. The numerical operations in such algorithms are generally implemented using finite-precision arithmetic, either fixed or floating point, most of which operate least-significant digit first. This results in a fundamental problem: if, after some time, the result has not converged, is this because we have not run the algorithm for enough iterations or because the arithmetic in some iterations was insufficiently precise? There is no easy way to answer this question, so users will often overbudget precision in the hope that the answer will always be to run for a few more iterations. We propose a fundamentally new approach: armed with the appropriate arithmetic able to generate results from most-significant digit first, we show that fixed compute-area hardware can be used to calculate an arbitrary number of algorithmic iterations to arbitrary precision, with both precision and iteration index increasing in lockstep. Thus, datapaths constructed following our principles demonstrate efficiency over their traditional arithmetic equivalents where the latter's precisions are either under-or over-budgeted for the computation of a result to a particular accuracy. For the execution of 100 iterations of the Jacobi method, we obtain a 1.60× increase in frequency and 15.7× LUT and 50.2× flip-flop reductions over a 2048-bit parallel-in, serial-out traditional arithmetic equivalent, along with 46.2× LUT and 83.3× flip-flop decreases versus the state-of-the-art online arithmetic implementation.

Digit Stability Inference for Iterative Methods Using Redundant Number Representation

“…For scenarios in which high-precision results are required, mixed-precision methods enabling performant and efficient implementation have been proposed [28]. In contrast to standard approaches, we adopt an MSD-first arbitrary-precision computation paradigm enabling iterative refinement limited only by memory capacity [2].…”

“…Speedups ranged from 2.0× (for η = 2 −4 ) to 2.2× (2 −1024 ). The saturation is due to properties of the arbitrary-precision arithmetic operators shared by both implementations, which require an increasing number of clock cycles to generate each digit as the significance of those digits decreases [2], [4]. As η falls, the increasing time per digit generation begins to dominate the gains realized through our new proposal's MSD elision.…”

“…. In our previous work, ARCHITECT, we introduced the first hardware architecture capable of computing solutions of systems of linear equations to arbitrary accuracy [2], [3], [4]. ARCHITECT uses redundant number representation to allow approximants to be computed from MSD first with online arithmetic, enabling earlier approximants to be refined as needed.…”

Digit Elision for Arbitrary-accuracy Iterative Computation

“…Without loss of generality, we used matrix size N = 2, radix r = 2, chunk width U = 8 and online delay δ Σ = 5 in this paper, constructing the datapath shown in Figure 4. This is identical in structure to that used in our previous work [1]. Digit sequencing and storage were realised using an FSM and memory architecture constructed as outlined in Section 4.…”

“…In our previous work, ARCHITECT [1]-the first method for implementing iterative computations to arbitrary accuracies in hardware-we addressed this issue. ARCHITECT employs online arithmetic, in which approximants are calculated starting from the most-significant digit (MSD).…”