Architectural design for next generation heterogeneous memory systems

Bivens, Alan; Dube, Parijat; Franceschini, Michele; Karidis, John; Lastras, Luis A.; Tsao, Mickey

doi:10.1109/imw.2010.5488395

Cited by 22 publications

(24 citation statements)

References 4 publications

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“…These requests are now served faster, and system performance and energy efficiency improves. 2 The crucial observation is that DRAM and PCM devices both employ row buffers which can be accessed at similar latencies and energies: application stall time (and average request latency) can be reduced if data which frequently misses in the row buffer is placed in DRAM as opposed to PCM, while placing data which frequently hits in the row buffer in PCM does not increase application stall time compared to placing that data in DRAM.…”

Section: Dram-pcm Hybrid Memory Systemsmentioning

confidence: 99%

“…Bivens et al [2] examined the various design concerns of a heterogeneous memory system such as memory latency, bandwidth, and endurance requirements of employing storage class memory (PCM, MRAM, Flash, etc.). Their hybrid memory organization is similar to ours and that in [24], in that DRAM is used as a cache to a slower memory medium, transparently to software.…”

Section: Energy Efficiencymentioning

confidence: 99%

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Row buffer locality aware caching policies for hybrid memories

Yoon

Meza

Ausavarungnirun

et al. 2012

2012 IEEE 30th International Conference on Computer Design (ICCD)

176

159

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Abstract-Phase change memory (PCM) is a promising technology that can offer higher capacity than DRAM. Unfortunately, PCM's access latency and energy are higher than DRAM's and its endurance is lower. Many DRAM-PCM hybrid memory systems use DRAM as a cache to PCM, to achieve the low access latency and energy, and high endurance of DRAM, while taking advantage of PCM's large capacity. A key question is what data to cache in DRAM to best exploit the advantages of each technology while avoiding its disadvantages as much as possible.We propose a new caching policy that improves hybrid memory performance and energy efficiency. Our observation is that both DRAM and PCM banks employ row buffers that act as a cache for the most recently accessed memory row. Accesses that are row buffer hits incur similar latencies (and energy consumption) in DRAM and PCM, whereas accesses that are row buffer misses incur longer latencies (and higher energy consumption) in PCM. To exploit this, we devise a policy that avoids accessing in PCM data that frequently causes row buffer misses because such accesses are costly in terms of both latency and energy. Our policy tracks the row buffer miss counts of recently used rows in PCM, and caches in DRAM the rows that are predicted to incur frequent row buffer misses. Our proposed caching policy also takes into account the high write latencies of PCM, in addition to row buffer locality.Compared to a conventional DRAM-PCM hybrid memory system, our row buffer locality-aware caching policy improves system performance by 14% and energy efficiency by 10% on data-intensive server and cloud-type workloads. The proposed policy achieves 31% performance gain over an all-PCM memory system, and comes within 29% of the performance of an all-DRAM memory system (not taking PCM's capacity benefit into account) on evaluated workloads.

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Section: Dram-pcm Hybrid Memory Systemsmentioning

confidence: 99%

Section: Energy Efficiencymentioning

confidence: 99%

Row buffer locality aware caching policies for hybrid memories

Yoon

Meza

Ausavarungnirun

et al. 2012

2012 IEEE 30th International Conference on Computer Design (ICCD)

176

159

View full text Add to dashboard Cite

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“…The cycle accurate architecture simulator GEM5 is a platform for research in the areas of operating systems, compilers, and computer architecture [20,10,22,46]. Simply put, GEM5 encompasses system-level architecture as well as processor micro-architecture.…”

Section: The Research Hypothesis and Our Researchmentioning

confidence: 99%

“…To explore a large variety of design alternatives, the system level design of real time computing systems demands effective and efficient computational methods for estimating execution time [39,19,46,11,35,5].…”

Section: Significance Of This Research and Our Contributionsmentioning

confidence: 99%

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A Regression Approach to Execution Time Estimation for Programs Running on Multicore Systems

Alshamlan¹

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Forming‐Free Resistive Switching of Electrochemical Titanium Oxide Localized Nanostructures: Anodization, Chemical Composition, Nanoscale Size Effects, and Memristive Storage

Tominov

Avilov

Вакулов

et al. 2022

Adv Elect Materials

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Electrochemical anodization is a powerful method for the preparation of oxide thin films with controlled thickness, structure, and composition and proves as a promising approach to be applied to memristive devices. Here, experimental studies on titanium oxide nanoscale structures produced by local anodic oxidation and the influence of the thickness on the memristive properties are presented. Controllable preparation of forming‐free memristive cells with switching voltages less than 3 V are demonstrated. The chemical composition and oxidation state of the elements in the TiOx nanostructures are analyzed by means of X‐ray photoelectron spectroscopy, which reveals the formation of TiO2 (458.4 eV), Ti2O3 (456.6 eV), and TiO (454.8 eV). The increasing thickness of the devices from 4.5 ± 0.7 to 7.9 ± 0.3 nm leads to a decrease in the OFF to ON resistance ratio from 250 to 10.7, respectively. The mechanism of formation and resistive switching in the anodic devices is also discussed. The results can be applied to the design and development of technological processes for memristive structure manufacturing based on electrochemical oxidation.

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Architectural design for next generation heterogeneous memory systems

Cited by 22 publications

References 4 publications

Row buffer locality aware caching policies for hybrid memories

Row buffer locality aware caching policies for hybrid memories

A Regression Approach to Execution Time Estimation for Programs Running on Multicore Systems

Forming‐Free Resistive Switching of Electrochemical Titanium Oxide Localized Nanostructures: Anodization, Chemical Composition, Nanoscale Size Effects, and Memristive Storage

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