Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators

Zulberti, Luca; Monopoli, Matteo; Nannipieri, Pietro; Fanucci, Luca

doi:10.1109/prime55000.2022.9816810

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Cited by 5 publications

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ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs

Luo,

Tan,

Agostini

et al. 2023

2023 60th ACM/IEEE Design Automation Conference (DAC)

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ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs

Luo,

Tan,

Agostini

et al. 2023

2023 60th ACM/IEEE Design Automation Conference (DAC)

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SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems

Zulberti,

Monorchio,

Monopoli

et al. 2024

2024 27th Euromicro Conference on Digital System Design (DSD)

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HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration

Chen,

Cai,

Zheng

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

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Coarse-grained reconfigurable arrays (CGRAs) are promising design choices in computation-intensive domains since they can strike a balance between energy efficiency and flexibility. A typical CGRA comprises processing elements (PEs) that can execute operations in applications and interconnections between them. Nevertheless, most CGRAs suffer from the ineffectiveness of supporting flexible architecture design and solving large-scale mapping problems. To address these challenges, we introduce HierCGRA, a novel framework that integrates hierarchical CGRA modeling, Chisel-based Verilog generation, LLVM-based data flow graph (DFG) generation, DFG mapping, and design space exploration (DSE). With the graph homomorphism (GH) mapping algorithm, HierCGRA achieves a faster mapping speed and higher PE utilization rate compared with the existing state-of-the-art CGRA frameworks. The proposed hierarchical mapping strategy achieves 41× speedup on average compared with the ILP mapping algorithm in CGRA-ME. Furthermore, the automated DSE based on Bayesian optimization achieves a significant performance improvement by the heterogeneity of PEs and interconnections. With these features, HierCGRA enables the agile development for large-scale CGRA and accelerates the process of finding a better CGRA architecture.

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Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators

Cited by 5 publications

References 12 publications

ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs

ML-CGRA: An Integrated Compilation Framework to Enable Efficient Machine Learning Acceleration on CGRAs

SmartDMA: Adaptable Memory Access Controller for CGRA-based Processing Systems

HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration

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