Architectural selection of A/D converters

Abstract

A method for the architectural selection of analog to digital (A/D) converters based on a generic figure of merit is described. First a figure of merit for the power consumption is introduced. This figure of merit includes both target specifications and technology data and has five generic parameters. The values of these generic parameters can be estimated by analyzing the different converter structures or by means of a fitting procedure using data from published designs. It is shown that the generic parameters have different values for different types of converters. Therefore the trade-off between speed, resolution, power dissipation and technology parameters depends on the type of converter. It is shown that the calculated figures of merit of the published designs, together with the calculated global trade-off comprise a surface in the (5 dimensional) design space. This surface makes it possible to accurately predict the power consumption and select the best converter solution for a certain target application. This can then serve as a first step in data converter synthesis or as a power estimator during high-level system design exploration.

Towards a highly-scalable wireless implantable system-on-a-chip for gastric electrophysiology

“…Therefore, the sampling rate of the ADC is 500×64 = 32 k sample-per-second (Sps) per 64 channels. Among different architectures, the successive approximation register (SAR) ADC is the most appropriate type for this application, considering the tradeoffs between the effective number of bits, required bandwidth, chip area, and power consumption [9].…”

Deterministic approaches to analog performance space exploration (PSE)

“…Many methods use performance models instead of circuit simulation for the sizing process [5,6,7,8,9,20,21,22,23,24]. Please note that this includes a preparation phase which again involves a large number of simulations.…”

“…with transistor netlists). This mixed behavioral-transistor level modeling of analog systems leads to a hierarchical design process, where system specifications are propagated top-down from the behavioral level to the transistor level [2,3,4,13,18,20,22,23,25,26,27,28]. Many of the current works aim at the automation of this well-known hierarchical design process.…”

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“…One major characteristic of performance macromodels is their short evaluation time compared to a circuit level simulator. Hence, they usually replace the circuit level simulator both to enhance early design space exploration [6], [1], [12] and to accelerate circuit sizing [7], [9]. The other characteristic is reusability.…”