Architecture-adaptive routability-driven placement for FPGAs

Sharma, Akshay; Hauck, Scott; Ebeling, Carl

doi:10.1109/fpl.2005.1515759

Cited by 29 publications

(31 citation statements)

References 13 publications

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“…We also note that when we do not route in the inner loop in the manner that works well for VPR , results of SA for the architectures considered in this manuscript are much worse; many placements are selected for which no routing solutions are available due to the highly restricted interconnect. Due to this reason, other SA mappers for CGRAs have also used a similar approach, with routing in the inner loop (Sharma et al, 2005). Simulated Annealing uses random numbers to determine which swaps to execute, and so results do vary from run to run.…”

Section: Our Simulated Annealing Algorithmmentioning

confidence: 99%

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Sistla¹,

Patel²,

Mehta³

2015

HCj

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One of the grand challenges in the design of portable/wearable electronics is to achieve optimal efficiency and flexibility in a tiny low power package. Coarse grained reconfigurable architectures (CGRAs) hold great promise for low power, high performance, and flexible designs for a domain of applications. CGRAs are very promising due to the ability to highly customize such architectures to an application domain. However, greater customization makes the mapping of applications onto these architectures very challenging. Good tools and fast, effective mapping algorithms are needed to support design space exploration for CGRAs. In particular, the mapping problem has been difficult to solve in a satisfying and general way. In this paper, we present an architectural design flow using crowdsourcing to provide mappings of benchmarks onto new architectures. We show that the crowd can provide high quality, reliable mappings, significantly outperforming our custom Simulated Annealing algorithm in almost all cases. We further show that the crowd can provide other types of feedback that are difficult to obtain from an automatic mapping algorithm. Our proof of concept cross-architectural study supports an 8Way or 4Way1Hop architecture as a top choice, concludes that a custom modification that constrains inputs and outputs consumes less energy but requires more area than its less constrained counterpart, and suggests that Stripe architectures are interesting to consider because they perform nearly as well as our mesh variants and may present a more straightforward mapping problem for the crowd or an automatic mapping algorithm.

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Section: Our Simulated Annealing Algorithmmentioning

confidence: 99%

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Sistla¹,

Patel²,

Mehta³

2015

HCj

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“…To do this, the FPGA CAD must meet the device routing capacity by targeting a hard channel width constraint. Since interconnect use of a design varies spatially with placement, this can be done by spreading out regions of peak demand to use fewer routing tracks but more CLBs [1][2][3] [4].…”

Section: Introductionmentioning

confidence: 99%

Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs

Tom

Leong

Lemieux

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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FPGA device area is dominated by interconnect, so low-cost FPGA architectures often have reduced interconnect capacity. This limited routing capacity creates a hard channel width constraint that can make it difficult for CAD tools to successfully map a circuit into these devices. Instead of migrating a design to a high-cost, resource-rich architecture that is easier to route, we present a cheaper alternative: a fully automated CAD flow (Un/DoPack) that finds local regions of high interconnect demand and reduces it by spreading out the logic in that region. This is done by introducing whitespace in the form of empty logic elements (LEs) within the configurable logic blocks (CLBs) of the congested region. After spreading, the congested region occupies more routing channels and so obtains access to greater aggregate interconnect capacity. Although this has the side effect of using more CLBs, it has the advantage of lowering peak interconnect demands and making a previously-unroutable circuit routable. We also design a new set of synthetic benchmark circuits that model interconnect variation within a large design. Using these benchmarks, we show that circuits with high interconnect variation require FPGA devices to have large channel widths. However, since congestion of such circuits is localized, Un/DoPack is very good at reducing the peak demands of circuits with high interconnect variation. Our results suggest that even for an average Rent exponent of 0.62 (a modest value), a large variation of this exponent within a design will also require FPGAs to have large channel widths. Thus, it is crucial to study interconnect variation of benchmark circuits when designing lowcost FPGAs. Previous research studying interconnect properties focuses on average Rent exponent values of each design, but we believe new work should study variation as well. For circuits with high interconnect variation, we demonstrate that channel widths can be reduced by up to ~40% with only ~10% increase in area.

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“…Sharma [18] proposed a placement algorithm that can explore FPGAs with arbitrary general interconnect. That work could be extended to target arbitrary interconnect within a logic block.…”

Section: Prior Workmentioning

confidence: 99%

“…The packing algorithm must determine if the internal connectivity within a logic block can successfully route the sections of the netlist that are assigned into that logic block. The packing algorithm in VTR [9], as with other prior attempts on supporting arbitrary interconnect [18] [20], employs heavy use of detailed routing to check for routability. This results in a packer that is often unnecessarily slow.…”

Section: Introductionmentioning

confidence: 99%

Towards interconnect-adaptive packing for FPGAs

Luu

Rose

Anderson

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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In order to investigate new FPGA logic blocks, FPGA architects have traditionally needed to customize CAD tools to make use of the new features and characteristics of those blocks. The software development effort necessary to create such CAD tools can be a time-consuming process that can significantly limit the number and variety of architectures explored. Thus, architects want flexible CAD tools that can, with few or no software modifications, explore a diverse space. Existing flexible CAD tools suffer from impractically long runtimes and/or fail to efficiently make use of the important new features of the logic blocks being investigated. This work is a step towards addressing these concerns by enhancing the packing stage of the open-source VTR CAD flow [17] to efficiently deal with common interconnect structures that are used to create many kinds of useful novel blocks. These structures include crossbars, carry chains, dedicated signals, and others. To accomplish this, we employ three techniques in this work: speculative packing, pre-packing, and interconnect-aware pin counting. We show that these techniques, along with three minor modifications, result in improvements to runtime and quality of results across a spectrum of architectures, while simultaneously expanding the scope of architectures that can be explored. Compared with VTR 1.0 [17], we show an average 12-fold speedup in packing for fracturable LUT architectures with 20% lower minimum channel width and 6% lower critical path delay. We obtain a 6 to 7-fold speedup for architectures with non-fracturable LUTs and architectures with depopulated crossbars. In addition, we demonstrate packing support for logic blocks with carry chains.

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Architecture-adaptive routability-driven placement for FPGAs

Cited by 29 publications

References 13 publications

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs

Un/DoPack: Re-Clustering of Large System-on-Chip Designs with Interconnect Variation for Low-Cost FPGAs

Towards interconnect-adaptive packing for FPGAs

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