Architecture and Implementation of Attribute Reduction Algorithm Using Binary Discernibility Matrix

Tiwari, Kanchan; Kothari, Ashwin

doi:10.1109/cicn.2011.42

Cited by 5 publications

(2 citation statements)

References 6 publications

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“…Hardware implementation of the reduct generation problem is described in [43]. Authors designed and implemented a reduct calculation block that utilizes the binary discernibility matrix and put them into the rough set processor used for the robotics application.…”

Section: Hardware Approaches For Finding Reductsmentioning

confidence: 99%

Breadth search strategies for finding minimal reducts: towards hardware implementation

Choromański

Grzes

Hońko

2020

Neural Comput & Applic

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Attribute reduction, being a complex problem in data mining, has attracted many researchers. The importance of this issue rises due to ever-growing data to be mined. Together with data growth, a need for speeding up computations increases. The contribution of this paper is twofold: (1) investigation of breadth search strategies for finding minimal reducts in order to emerge the most promising method for processing large data sets; (2) development and implementation of the first hardware approach to finding minimal reducts in order to speed up time-consuming computations. Experimental research showed that for software implementation blind breadth search strategy is in general faster than frequency-based breadth search strategy not only in finding all minimal reducts but also in finding one of them. An inverse situation was observed for hardware implementation. In the future work, the implemented tool is to be used as a fundamental module in a system to be built for processing large data sets.Keywords Attribute reduction Á Minimal reducts Á Breadth search strategy Á Hardware implementation Á Field programmable gate arrays Neural Computing and Applications https://doi.org/10.1007/s00521-020-04833-7( 0123456789().,-volV) (0123456789(). ,-volV)Publisher's Note Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Neural Computing and Applications

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Section: Hardware Approaches For Finding Reductsmentioning

confidence: 99%

Breadth search strategies for finding minimal reducts: towards hardware implementation

Choromański

Grzes

Hońko

2020

Neural Comput & Applic

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“…Tiwari et.al in their work [27] presented architecture for computing reduct using binary discernibility matrix. They have used Xilinx software and Spartan 3 FPGA.…”

Section: G Kstiwari's Etal Hardware Implementationmentioning

confidence: 99%

Design and Implementation of Rough Set Algorithms on FPGA: A Survey

Tiwari¹,

Kothari²

2014

ijarai

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Abstract-Rough set theory, developed by Z. Pawlak, is a powerful soft computing tool for extracting meaningful patterns from vague, imprecise, inconsistent and large chunk of data. It classifies the given knowledge base approximately into suitable decision classes by removing irrelevant and redundant data using attribute reduction algorithm.Conventional Rough set information processing like discovering data dependencies, data reduction, and approximate set classification involves the use of software running on general purpose processor. Since last decade, researchers have started exploring the feasibility of these algorithms on FPGA. The algorithms implemented on a conventional processor using any standard software routine offers high flexibility but the performance deteriorates while handling larger real time databases. With the tremendous growth in FPGA, a new area of research has boomed up. FPGA offers a promising solution in terms of speed, power and cost and researchers have proved the benefits of mapping rough set algorithms on FGPA. In this paper, a survey on hardware implementation of rough set algorithms by various researchers is elaborated.

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