Architecture-Aware Approximate Computing

Abstract

Deliberate use of approximate computing has been an active research area recently. Observing that many application programs from different domains can live with less-than-perfect accuracy, existing techniques try to trade off program output accuracy with performance-energy savings. While these works provide point solutions, they leave three critical questions regarding approximate computing unanswered, especially in the context of dropping/skipping costly data accesses: (i) what is the maximum potential of skipping (i.e., not performing) data accesses under a given inaccuracy bound?; (ii) can we identify the data accesses to drop randomly, or is being architecture aware (i.e., identifying the costliest data accesses in a given architecture) critical?; and (iii) do two executions that skip the same number of data accesses always result in the same output quality (error)? This paper first provides answers to these questions using ten multithreaded workloads, and then, motivated by the negative answer to the third question, presents a program slicing-based approach that identifies the set of data accesses to drop such that (i) the resulting performance/energy benefits are maximized and (ii) the execution remains within the error (inaccuracy) bound specified by the user. Our slicing-based approach first uses backward slicing and then forward slicing to decide the set of data accesses to drop. Our experimental evaluations using ten multithreaded workloads show that, when averaged over all benchmark programs we have, 8.8% performance improvement and 13.7% energy saving are possible when we set the error bound to 2%, and the corresponding improvements jump to 15% and 25%, respectively, when the error bound is raised to 4%.

Approximate execution and grouping of critical sections for performance‐accuracy tradeoff

“…20 Karakoy et al propose an approach to skip data accesses such that performance benefits are maximized and error is bounded by user-defined level. 21 Brand et al propose "anytime" floating point instructions that compute only a predefined number of most significant bits. 22 The number of computed bits is embedded into the instruction and the resulting floating number still has the same number of precision bits.…”

“…Yazdanbakhsh et al propose an implementation that predicts the value of miss operations, and if they can be safely approximated 20 . Karakoy et al propose an approach to skip data accesses such that performance benefits are maximized and error is bounded by user‐defined level 21 . Brand et al propose “anytime” floating point instructions that compute only a predefined number of most significant bits 22 .…”

Data Transfer API and its Performance Model for Rank-Level Approximate Computing on HPC Systems

“…Karakoy et al proposed a slicing-based approach to reduce memory access while ensuring that accuracy lies within the specified error bound [8]. Shafique et al implemented open-source libraries of AC-enabled arithmetic components to develop AC-enabled systems considering multiple system layers (from logic to architecture) simultaneously [13].…”

“…[6] focuses on FPGA utilization for AC but does not consider differences among ranks. [8] utilizes optical interconnect for lower latency by allowing soft errors; however, it assumes error-tolerant applications only. To expand the scope of AC techniques for HPC systems, it is important to consider characteristics of parallel threads/ranks and communication among them.…”