Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors

Abstract

Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications.In this paper, we design and embed several architecture-aware optimizations into a multi-threaded general matrix multiplication (gemm), a key operation of the BLAS, in order to obtain a high performance implementation for ARM big.LITTLE AMPs. Our solution is based on the reference implementation of gemm in the BLIS library, and integrates a cache-aware configuration as well as asymmetric-static and dynamic scheduling strategies that carefully tune and distribute the operation's micro-kernels among the big and LITTLE cores of the target processor. The experimental results on a Samsung Exynos 5422, a system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric scheduling attain important Email addresses: catalans@uji.es (Sandra Catalán), figual@ucm.es (Francisco D. Igual), mayo@uji.es (Rafael Mayo), rarodrig@uji.es (Rafael Rodríguez-Sánchez), quintana@uji.es (Enrique S. Quintana-Ortí)gains in performance with respect to its architecture-oblivious counterparts while exploiting all the resources of the AMP to deliver considerable energy efficiency.

Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operations

“…• In conclusion, compared with previous work [13,15], this paper demonstrates that, for the particular domain of DLA, it is possible to hide the difficulties intrinsic to dealing with an asymmetric architecture (e.g., workload balancing for performance, energy-aware mapping of tasks to cores, and criticality-aware scheduling) inside an asymmetry-aware implementation of the BLAS-3. As a consequence, our solution can refactor any conventional (asymmetry-agnostic) scheduler to exploit the task parallelism present in complex DLA operations.…”

“…These studies offered a few relevant insights that guided the parallelization of gemm (and also other Level-3 BLAS) on the ARM big.LITTLE architecture under the GTS software execution model. Concretely, the architecture-aware multi-threaded parallelization of gemm in [13] integrates the following three techniques:…”

“…To close this section, we emphasize that our work differs from [13,15] in that we address sophisticated DLA operations, with a rich hierarchy of task dependencies, by leveraging a conventional runtime scheduler in combination with a data-parallel asymmetryconscious implementation of the BLAS-3.…”

“…• For this particular factorization, we describe how to leverage the asymmetryoblivious task-parallel runtime scheduler in OmpSs, in combination with a dataparallel instance of the BLAS-3 (basic linear algebra subprograms) [12] in the BLIS library specifically designed for ARM big.LITTLE AMPs [13,14].…”

Energy balance between voltage-frequency scaling and resilience for linear algebra routines on low-power multicore architectures

“…The approach parallelizes the nested five-loop organization of gemm at one or more levels (i.e., loops), taking into account the cache organization of the target platform, the granularity of the computations, and the risk of race conditions, among other factors. For the multicore processors targeted in this work, an efficient choice is to extract the parallelism from Loop 4 only [26] via, e.g., OpenMP.…”