2012
DOI: 10.1016/j.protcy.2012.10.044
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Architecture Design and FPGA Implementation of CORDIC Algorithm for Fingerprint Recognition Applications

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Cited by 2 publications
(3 citation statements)
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“…Figure 5 shows the architecture of the improved atan-CORDIC with the fast magnitude estimator and the input magnification. A difference compared to other CORDIC optimizations and CORDIC architectures in the literature [7][8][9][14][15][16] is the maintenance of the standard CORDIC core, to which we add a low-complexity pre-processing unit, working on the input ranges, thus minimizing the overall circuit complexity overhead. When the Mk area for a point is known, a shift factor (SFk) is selected and applied to the x 0 and y 0 input coordinates in a way that the magnified coordinates reach the M1 area or the M2 area.…”
Section: Fast Magnitude Estimator and Improved Cordic Architecturementioning
confidence: 99%
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“…Figure 5 shows the architecture of the improved atan-CORDIC with the fast magnitude estimator and the input magnification. A difference compared to other CORDIC optimizations and CORDIC architectures in the literature [7][8][9][14][15][16] is the maintenance of the standard CORDIC core, to which we add a low-complexity pre-processing unit, working on the input ranges, thus minimizing the overall circuit complexity overhead. When the Mk area for a point is known, a shift factor (SFk) is selected and applied to the x 0 and y 0 input coordinates in a way that the magnified coordinates reach the M1 area or the M2 area.…”
Section: Fast Magnitude Estimator and Improved Cordic Architecturementioning
confidence: 99%
“…For example, it is at the core of the phase calculation of complex-envelope signals from the in-phase and quadrature components in communication systems, or for angular position measurement in automotive applications, or for phase computation in power systems control and in AC circuit analysis [5][6][7][8][9]. Although the standard CORDIC algorithm is well known in literature, its efficient implementation in terms of computation accuracy and with low overheads in terms of circuit complexity and power consumption is still an open issue [6][7][8][9][10][11][12][13][14][15][16]. To this aim, both full-custom (ASIC in [6]) and semi-custom (IP macrocells synthesizable on FPGA or standard-cell technologies in [8,9,16]) approaches have been followed in the literature.…”
Section: Introductionmentioning
confidence: 99%
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