Architecture for simulation-based performance assessment of planning approaches in semiconductor manufacturing

Ponsignon, Thomas; Monch,

doi:10.1109/wsc.2010.5679025

Cited by 13 publications

(3 citation statements)

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“…In this paper, we make a first attempt to mitigate this assumption by considering an iterative simulation scheme. Note that the decision to look at an iterative scheme was influenced by the fact that we can reuse the simulation infrastructure that is described by Mönch and Zimmermann (2004) and Ponsignon and Mönch (2010).…”

Section: Discussion Of Related Workmentioning

confidence: 99%

“…We use the infrastructure for iterative simulation that is described by Mönch and Zimmermann (2004) and that was later extended to the simulation of supply chains by Ponsignon and Mönch (2010). The center point of this architecture is a blackboard-type data layer between an AutoSched AP simulation model of the one-stage supply chain and the master planning heuristic.…”

Section: Implementation Issuesmentioning

confidence: 99%

“…Non-critical machines are represented by stochastic delays using a Gamma distribution in the process flows of the lots. A similar approach is used in Ponsignon and Mönch (2010).…”

Section: Simulation Model Usedmentioning

confidence: 99%

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Using iterative simulation to incorporate load-dependent lead times in master planning heuristics

Ponsignon

Mönch

2012

Proceedings Title: Proceedings of the 2012 Winter Simulation Conference (WSC)

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In this paper, we consider heuristics for master planning in semiconductor manufacturing. While lead times are typically assumed as fixed in production planning, we use iterative simulation to take loaddependent lead times into account. An AutoSched AP simulation model of a semiconductor supply chain is used for implementing the scheme. Simulation results show that the iterative scheme converges fast and leads to less variable, more profitable production plans compared to planes obtained by the fixed lead time approach. INTRODUCTIONProduction planning deals with determining release schedules that try to match production output with given demand in such a way that revenue-or cost-related objective functions are optimized while capacity restrictions are taken into account. Most of the existing production planning models assume a fixed lead time as an exogenous, prescribed parameter of the planning approach (Voß and Woodruff 2006). The lead time of a product is an estimate of the cycle time in the planning algorithms. We refer to the cycle time of a product, also known as flow time, as the average time that is required to complete its processing in the production system. Production planning in semiconductor manufacturing is challenging due to the reentrant flows, the long cycle times, the high utilization of the expensive machines, the diverse product mix, and the different sources of variability. It is well known from queueing theory that the cycle time increases nonlinearly with the utilization of the resources of the base system. However, the utilization is a result of the release schedule used. This leads to a well-known circularity in production planning. On the one hand, the planning approach determines the release schedule based on a prescribed lead time. On the other hand, the cycle time depends on the lot release schedule (Pahl et al. 2007, Missbauer andUzsoy 2011).Iterative simulation is one approach that tackles this circularity by iterating between a production planning model that determines production quantities based on a prescribed lead time and a discrete-event simulation model that uses these production quantities to calculate new flow time estimates (Hung and Leachman 1996, Almeder et al. 2009, Irdem et al. 2010.In this paper, we are interested in applying the iterative simulation approach to a specific multifacility, multi-product, and multi-period master planning problem. The problem includes important features of semiconductor supply chains like reentrant process flows, outsourcing options, and multiple products with long process flows. The master planning problem and exact and heuristic approaches to efficiently solve it are discussed by the two present authors in (Ponsignon and Mönch 2012). However, a fixed lead time is assumed for all products in this paper. A one-stage supple chain consisting of four scaled-down wafer fabs is represented by a simulation model. To the best of our knowledge, iterative 978-1-4673-4781-5/12/$31.00 ©2012 IEEE

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Section: Discussion Of Related Workmentioning

confidence: 99%

Section: Implementation Issuesmentioning

confidence: 99%