Architecture implementation using the machine description language LISA

Schliebusch, Oliver; Hoffmann, Andreas; Nohl, Achim; Braun, Gunnar; Meyr, H.

doi:10.1109/aspdac.2002.994928

Cited by 43 publications

(33 citation statements)

References 10 publications

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“…Since we are only interested in the latter, our architecture specification can be simplified considerably. Furthermore, few ADLs provide a path to synthesis through RTL generation, and for those that do [27,47,56] the resulting RTL is often a very high-level description (for example, in SystemC), and therefore depends heavily on synthesis tools to optimize the design. For example, Mishra [27] provided RTL generation for the EXPRESSION ADL and discovered that the automatically generated RTL incurred 20% more area, 52% more power, and 28% slower clock frequency than an equivalent processor which was coded behaviourally for the purpose of cycle accurate [45,55,56] system+micro yes (generated) sim, asm PICO [26] system+ micro yes (generated) comp, sim simulation.…”

Section: Adl-based Architecture Exploration Environmentsmentioning

confidence: 99%

The microarchitecture of FPGA-based soft processors

Yiannacouras

Rose

Steffan

2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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As more embedded systems are built using FPGA platforms, there is an increasing need to support processors in FPGAs. One option is the soft processor, a processor implemented in the reconfigurable logic of the FPGA. Commercial soft processors have been widely deployed, and hence we are motivated to understand their microarchitecture. We must re-evaluate microarchitecture in the soft processor context because an FPGA platform is significantly different than an ASIC platform. This dissertation presents an infrastructure for rapidly generating RTL models of soft processors, as well as a methodology for measuring their area, performance, and power. Using the automatically-generated soft processors we explore many interesting microarchitectural axes in the trade-off space. We also compare our designs to Altera's Nios II commercial soft processors and find that our automatically generated designs span the design space while remaining very competitive.ii

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Section: Adl-based Architecture Exploration Environmentsmentioning

confidence: 99%

The microarchitecture of FPGA-based soft processors

Yiannacouras

Rose

Steffan

2005

Proceedings of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

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“…Together with our previous work on automatic synthesis of instruction encoding [13] and generation of RTL descriptions [16], the proposed semantic extension of the LISA ADL allows for a very high design efficiency on abstract level, while maintaining consistency by means of a single model throughout the entire design process.…”

Section: Resultsmentioning

confidence: 99%

“…This is due to the generic implementation of the micro-operation behavior in the library, which contains a non-negligible overhead for native bit-widths, i.e., 8,16, and 32-bit data. Although the overall design efficiency is much increased due to the enormous reduction in design effort, there is no doubt that the micro-operation library can be optimized in order to meet the performance of the BEHAVIOR-generated simulator.…”

Section: Simulation Performancementioning

confidence: 99%

A novel approach for flexible and consistent ADL-driven ASIP design

Braun¹,

Nohl²,

Sheng³

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

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Architecture description languages (ADL) have been established to aid the design of application-specific instruction-set processors (ASIP). Their main contribution is the automatic generation of a software toolkit, including C compiler, assembler, linker, and instruction-set simulator. Hence, the challenge in the design of such ADLs is to unambiguously capture the architectural information required for the toolkit generation in a single model. This is particularly difficult for C compiler and simulator, as both require information about the instructions' semantics, however, while the C compiler needs to know what an instructions does, the simulator needs to know how. Existing ADLs solve this problem by either introducing redundancy or by limiting the language's flexibility. This paper presents a novel, mixed-level approach for ADLbased instruction-set description, which offers maximum flexibility while preventing from inconsistencies. Moreover, it enables capturing instruction-and cycle-accurate descriptions in a single model. The feasibility and design efficiency of our approach is demonstrated with a number of contemporary, real-world processor architectures.

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“…For example, nML is extended by Target Compiler Technologies [16] to perform synthesis and test generation. Similarly, the LISA language has been used for hardware generation [54,67], instruction encoding synthesis [68] and JTAG interface generation [69]. Likewise, EXPRESSION has been used for hardware generation [56], instruction set synthesis [70], test generation [64,71], and specification validation [58,62].…”

Section: Discussionmentioning

confidence: 99%

“…The synthesisable HDL generation approach based on the LISA language [53] produces an HDL model of the architecture. The designer has the choice to generate a VHDL, Verilog or SystemC representation of the target architecture [54]. The HDL generation methodology presented by Mishra et al [55,56] combines the advantages of the processor template based environments and the language based specifications using EXPRESSION ADL.…”

Section: Generation Of Hardware Implementationmentioning

confidence: 99%

Processor Description Languages

Mishra¹,

Dutt²

2008

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Embedded systems present a tremendous opportunity to customise designs by exploiting the application behaviour. Shrinking time-to-market, coupled with short product lifetimes, create a critical need for rapid exploration and evaluation of candidate architectures. Architecture description languages (ADL) enable exploration of programmable architectures for a given set of application programs under various design constraints such as area, power and performance. The ADL is used to specify programmable embedded systems, including processor, coprocessor and memory architectures. The ADL specification is used to generate a variety of software tools and models facilitating exploration and validation of candidate architectures. The paper surveys the existing ADLs in terms of (a) the inherent features of the languages and (b) the methodologies they support to enable simulation, compilation, synthesis, test generation and validation of programmable embedded systems. It concludes with a discussion of the relative merits and demerits of the existing ADLs and expected features of future ADLs.

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Architecture implementation using the machine description language LISA

Abstract: Abstract

Cited by 43 publications

References 10 publications

The microarchitecture of FPGA-based soft processors

The microarchitecture of FPGA-based soft processors

A novel approach for flexible and consistent ADL-driven ASIP design

Processor Description Languages

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