Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC

Ahmad, B.; Erdogan, A.T.; Khawam, S.

doi:10.1109/ahs.2006.25

Cited by 52 publications

(12 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Nollet at al. [17] developed a run-time resource management scheme that is able to efficiently manage a NoC containing fine grain reconfigurable hardware tiles, while in [2] a dynamically reconfigurable NoC architecture is proposed for reconfigurable multiprocessor System-on-Chip (MPSoC), with the aim to satisfy increased communication needs, low cost of the silicon implementation, Quality of Service and scalability.…”

Section: Related Workmentioning

confidence: 99%

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Fiorin

Luković

Palermo³

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

View full text Add to dashboard Cite

show abstract

Section: Related Workmentioning

confidence: 99%

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Fiorin

Luković

Palermo³

2008

2008 IEEE International Symposium on Parallel and Distributed Processing

View full text Add to dashboard Cite

show abstract

“…An approach was proposed in [1] to allow NoC to dynamically configure itself with respect to the switching modes with the changing communication requirements of the system at run time. The main objective of this approach is to provide low latency, low power, and high data throughput.…”

Section: Related Workmentioning

confidence: 99%

Towards a bio-inspired architecture for autonomic network-on-chip

Bakhouya

2010

2010 International Conference on High Performance Computing &Amp; Simulation

View full text Add to dashboard Cite

show abstract

“…The first and more widely adopted approach involves adding reconfiguration logic to the network interfaces (NIs) and routers but the logic consumes extra area [7][8] [9]. The second and more recent method requires the use of partially reconfigurable FPGA devices such as the Xilinx Virtex series.…”

Section: Introductionmentioning

confidence: 99%

An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay

Hoo

Kumar

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

With the increasing number of processors in Multiprocessor System-on-Chips (MPSoCs), Network-on-Chips (NoCs) are replacing conventional buses as the interprocessor communication architecture. Since different use cases might be running on MPSoCs, there is a need for dynamically reconfigurable NoC. However, most dynamically reconfigurable NoCs have a large area overhead due to the additional reconfiguration logic. While recently some dynamically reconfigurable NoCs have been proposed based on partial reconfiguration (PR), they have high reconfiguration delay and require off-line bitstream generation for all possible scenarios. The problem lies with the design of the crossbar switch, which is the fundamental component of a NoC. In this paper, a novel partially reconfigurable crossbar switch design with low area requirement, low reconfiguration delay and runtime bitstream generation is presented. The crossbar switch is built from lookup tables (LUTs), and reconfiguration is done by modifying the LUTs' content through PR. Reconfiguration delay is minimized by constraining the placement of the LUTs into the least number of configurable logic block columns and identifying the configuration frames that are responsible for LUTs' content. The novel crossbar switch design achieves an area saving of up to 84% and reconfiguration delay minimization of up to 78%. It can be used to realize any network topology, and Clos, Benes and single stage crossbar topologies are evaluated in the paper.

show abstract

Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC

Cited by 52 publications

References 8 publications

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Implementation of a reconfigurable data protection module for NoC-based MPSoCs

Towards a bio-inspired architecture for autonomic network-on-chip

An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay

Contact Info

Product

Resources

About