Architecture of a message-driven processor

Dally, William J.; Chao, Ling; Chien, Andrew A.; Hassoun, Soha; Horwat, Waldemar; Kaplan, Jon; Song, Paul; Totty, Brian; Wills, Scott

doi:10.1145/285930.285993

Cited by 44 publications

(6 citation statements)

References 6 publications

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“…Bracy et al discuss these lightweight user-level interrupts and utilize existing coherency logic to provide simple, preemptive, low-latency communication between cores [5]. Many other microarchitectures also support preemptive communication [2,7,13,14,22,24,29,35,37].…”

Section: Related Workmentioning

confidence: 99%

Pangaea

Wong

Bracy

Schuchman

et al. 2008

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques

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Moore's Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneous CMP design for non-rendering workloads that integrates IA32 CPU cores with non-IA32 GPU-class multicores, extending the current state-of-the-art CPU-GPU integration that physically "fuses" existing CPU and GPU designs. Pangaea introduces (1) a resource repartitioning of the GPU, where the hardware budget dedicated for 3Dspecific graphics processing is used to build more generalpurpose GPU cores, and (2) a 3-instruction extension to the IA32 ISA that supports tighter architectural integration and fine-grain shared memory collaborative multithreading between the IA32 CPU cores and the non-IA32 GPU cores. We implement Pangaea and the current CPU-GPU designs in fully-functional synthesizable RTL based on the production quality RTL of an IA32 CPU and an Intel GMA X4500 GPU. On a 65 nm ASIC process technology, the legacy graphics-specific fixed-function hardware has the area of 9 GPU cores and total power consumption of 5 GPU cores. With the ISA extensions, the latency from the time an IA32 core spawns a GPU thread to the time the thread begins execution is reduced from thousands of cycles to fewer than 30 cycles. Pangaea is synthesized on a FPGA-based prototype and runs off-the-shelf IA32 OSes. A set of general-purpose non-graphics workloads demonstrate speedups of up to 8.8×.

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Section: Related Workmentioning

confidence: 99%

Pangaea

Wong

Bracy

Schuchman

et al. 2008

Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques

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“…The major difference between SSB and the classical tagged memory (e.g. full/empty bits) in HEP [38], Tera [5], MDP [13], Sparcle [3], M-Machine [24], the MT processor in Eldorado [18], and other machines, has been explained in Section 1. Istructure [6] memory system employed in some dataflow model based architectures [6,23] exploits similar design as full/empty bits based memory system.…”

Section: Related Workmentioning

confidence: 99%

“…For instance, HEP [38], Tera [5], MDP [13], Sparcle [3], M-Machine [24], the MT processor in Eldorado [18], and others use hardware bits as tags (e.g., full/empty bits) to support word-level fine-grain synchronization. These designs tag the entire memory by associating additional access state bits with each word in memory.…”

Section: Introductionmentioning

confidence: 99%

Synchronization state buffer

Zhu

Sreedhar

et al. 2007

Proceedings of the 34th Annual International Symposium on Computer Architecture

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Efficient fine-grain synchronization is extremely important to effectively harness the computational power of many-core architectures. However, designing and implementing finegrain synchronization in such architectures presents several challenges, including issues of synchronization induced overhead, storage cost, scalability, and the level of granularity to which synchronization is applicable. This paper proposes the Synchronization State Buffer (SSB), a scalable architectural design for fine-grain synchronization that efficiently performs synchronizations between concurrent threads. The design of SSB is motivated by the following observation: at any instance during the parallel execution only a small fraction of memory locations are actively participating in synchronization. Based on this observation we present a finegrain synchronization design that records and manages the states of frequently synchronized data using modest hardware support. We have implemented the SSB design in the context of the 160-core IBM Cyclops-64 architecture. Using detailed simulation, we present our experience for a set of benchmarks with different workload characteristics.

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“…Cascading of RAPS works as follows: A general purpose node such as a MDP [2] sets up the pipeline by loading methods and templates into the appropriate RAP chips. A C+E message is then sent to the first RAP in the pipeline to begin the calculation.…”

Section: Templatesmentioning

confidence: 99%

“…It includes the necessary control mechanisms and message handling capabilities to fit into the system. The RAP borrows several ideas that were first developed in the Message Driven Processor (MDP) [2] which is the general purpose computing node for the sys&m. In particular the RAP executes messages directly, reducing message interpretation overhead, and it makes use of the same network communication scheme [4] [5].…”

Section: Introductionmentioning

confidence: 99%

The reconfigurable arithmetic processor

Fiske¹,

Dally²

[1988] the 15th Annual International Symposium on Computer Architecture. Conference Proceedings

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The Reconfigurable Arithmetic Processor (RAP) is an arithmetic processing node for a message-passing, MIMD concurrent computer. It incorporates on one chip several serial, 64 bit floating point arithmetic units connected by a switching network. By sequencing the switch through different patterns, the RAP chip calculates complete arithmetic formulas. By chaining together its arithmetic units the RAP reduces the amount of off chip data transfer: in the examples we have simulated off chip 1/0 can often be reduced to 30% or 40% of that required by a conventional arithmetic chip. Simulations predict a peak performance of 2OMFlops with 800Mbit/sec off chip bandwidth in a 2pm CMOS process.

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Architecture of a message-driven processor

Cited by 44 publications

References 6 publications

Pangaea

Pangaea

Synchronization state buffer

The reconfigurable arithmetic processor

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