Architecture of a reconfigurable low power gigabit ATM switch

Abstract

Multistage switch interconnects like banyan switches are preferred in high speed networks for their cascadable structure and suitability for V U 1 implementation. However most of these switch implementations are monolithic in nature and do not provide flexibility of dynamic re-routing of cells from active ports through idle ports. In this paper we take a critical look at a basic 8 x 8 benes switch from the perspective of identifying smaller blocks which can be pipelined in space and temporally multiplexed to exploit hardware reuse. A topological analysis of a 8 x 8 benes switch is carried out to identifr mutually exclusive path sets that can be overlayed for hardware reuse. Based on this analysis we arrive at a basic building block called X-Structure, using which a 8 x 8 switch is constructed. The X-structure supports dynamic re-routing of cells and power down mode. A communication controller is designed using the the X-Structure based ATM switch at its core. A pevormance evaluation of the switch indicates a power saving of 66.66% due to hardware reuse, an 18.6% increase in hardware utilization and an aggregate throughput of 2.66 Gbps for a 8 x 8 switch.