Architecture of Computing System based on Chiplet

Abstract

Computing systems are widely used in medical diagnosis, climate prediction, autonomous vehicles, etc. As the key part of electronics, the performance of computing systems is crucial in the intellectualization of the equipment. The conflict between performance, efficiency, and cost can be solved by choosing an appropriate computing system architecture. In order to provide useful advice and instructions for the designers to fabricate high-performance computing systems, this paper reviews the Chiplet-based computing system architectures, including computing architecture and memory architecture. Firstly, the computing architecture used for high-performance computing, mobile, and PC is presented and summarized. Secondly, the memory architecture based on mainstream memory and emerging non-volatile memory used for data storing and processing are introduced, and the key parameters of memory are compared and discussed. Finally, this paper is concluded, and the future perspectives of computing system architecture based on Chiplet are presented.

Design of Spectrum Processing Chiplet Based on FFT Algorithm

“…As the semiconductor industry enters the post-Moore era, the chiplet has received widespread attention due to its high performance, low power consumption, high area utilization, low cost, and reusability, and is considered as one of the key development directions for future integrated circuits [ 10 , 11 ]. Therefore, we propose a chiplet-based implementation of the FFT algorithm, whose implementation process is essentially similar to that of an ASIC, without the need to pursue extreme feature sizes while ensuring proper functionality.…”

Application and Prospect of Artificial Intelligence Methods in Signal Integrity Prediction and Optimization of Microsystems

“…With the development requirements of 5G, Internet of Things (IoT), and artificial intelligence (AI) for intelligent and high-performance electronic systems, electronic systems are developing towards high performance, miniaturization, and intelligence, and have been widely used in high-performance computing, smart medical care, autonomous driving, IoT, smart wear and additional devices [ 1 , 2 , 3 , 4 , 5 ]. However, as the miniaturization of feature size gradually approaches the atomic limit, the principle of improving chip performance along Mole’s law gradually fails [ 6 , 7 , 8 ].…”

Layout Dependence Stress Investigation in through Glass via Interposer Architecture Using a Submodeling Simulation Technique and a Factorial Design Approach

“…In the chiplet integration design, the microbump, through via, and redistribution layer (RDL) are still regarded as the major interconnection components in 2.5D integration technology [ 35 ]. Multilayer RDL interposer packaging is regarded as a promising solution for heterogeneous integration platforms; six-layer interconnection is provided for design flexibility of chiplets and high bandwidth integration in this solution [ 36 ].…”