Architecture Specifications in CλaSH

Kuper, Jan; Baaij, Christiaan; Kooijman, Matthijs; Gerards, Marco E. T.

doi:10.1007/978-1-4614-1427-8_12

Cited by 5 publications

(4 citation statements)

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“…CλaSH [157][158][159] is another example of functional resource description which is based on Haskell. Using an efficient resource description language might help to increase the total performance of the constructed simulators.…”

Section: Speed Vs Accuracymentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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This is the accepted version of the paper.This version of the publication may differ from the final published version. Permanent repository link AbstractThe architecture design of peta-scale computing systems is complex and presents lots of difficulties to designs, as current tools lack support for relevant features of future scenarios. Novel systems must be designed with great care and tools, such as manycore architecture simulators, must be adapted accordingly. However, current simulation tools are very slow, often specific-purposeoriented, suffer from various issues and are rarely able to simulate thousands of cores. The emergence of peta-scale systems and the upcoming manycore era brings nevertheless new challenges to computing systems and architectures, adding further difficulties and requirements on the development of the corresponding simulators. Furthermore, the design of architecture simulators for manycore systems involve methods and techniques from various interdisciplinary research areas, which in turn brings more challenges in different aspects. As system complexity grows, the growth of the simulation capacity is being outpaced (reaching the so called simulation wall). In this paper, we present the challenges for simulating future large scale manycore environments, and we investigate the adequacy of current modeling and simulation tools, methodologies and techniques. The aim of this work is to highlight how current approaches can best deal with the identified problems, smoothing the challenges of research in future peta-scale systems.

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Section: Speed Vs Accuracymentioning

confidence: 99%

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Zarrin

Aguiar

Barraca

2017

Simulation Modelling Practice and Theory

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“…It is directly integrated into ghc [5], an open source Haskell compiler. A detailed description of the working principle of CλaSH can be found in [1], several design examples in [6]. The idea behind CλaSH is that electronic circuits can be seen as a mathematical function: For a certain set of inputs, a determined output is produced.…”

Section: Designing Hardware Using Haskell and Thementioning

confidence: 99%

Designing a dataflow processor using CλaSH

et al. 2010

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Abstract-In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code. The VHDL code was synthesised with 90 nm TSMC libraries and placed and routed. Simulation of the final netlist showed correct behaviour. We conclude that Haskell and CλaSH are well-suited to define hardware on a very high level of abstraction which is close to the mathematical description of the desired architecture. By using CλaSH, the designer does not have to care about internal implementation details like when designing with VHDL. The complete processor was described in 300 lines of code, some snippets are shown as illustration.

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“…Because of these reasons, it is natural to use functional programming languages to design synchronous digital hardware. In [1], [2] we have introduced a modified subset of Haskell, together with a compiler called CλaSH, which is based on the Glasgow Haskell Compiler (GHC).…”

Section: Introductionmentioning

confidence: 99%

Higher-Order Abstraction in Hardware Descriptions with C?aSH

Gerards

Baaij

Kuper

et al. 2011

2011 14th Euromicro Conference on Digital System Design

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Synchronous hardware can be straightforwardly modelled as a function from input and (current) state to an updated state and output. The CλaSH compiler can translate such a transition function, described in a functional language, to synthesisable VHDL. Taking a hardware-oriented viewpoint, components can then be seen as an instantiation of such a transition function. An abstraction called Arrows is used to directly model components by combining a transition function and its state. The abstraction also provides an uniform interface for composition, without losing the referential transparency offered by a functional description. Furthermore, readability of hardware designs is increased by the use of the γ-syntax, that automatically composes components according to the Arrow interface. The advantages of the Arrow abstraction and the γ-syntax are demonstrated by means of a realistic example circuit consisting of multiple components. This is a significant extension to CλaSH and enables many high level abstractions.

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Architecture Specifications in CλaSH

Cited by 5 publications

References 5 publications

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Designing a dataflow processor using CλaSH

Higher-Order Abstraction in Hardware Descriptions with C?aSH

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Architecture Specifications in CλaSH

Cited by 5 publications

References 5 publications

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects

Designing a dataflow processor using C&#x03BB;aSH

Higher-Order Abstraction in Hardware Descriptions with C?aSH

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Designing a dataflow processor using CλaSH