Are We There Yet? A Study on the State of High-Level Synthesis

Lahti, Sakari; Sjövall, Panu; Vanne, Jarno; Hämäläinen, Timo D.

doi:10.1109/tcad.2018.2834439

Cited by 111 publications

(56 citation statements)

References 60 publications

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“…46 articles were studied on the quality of the results and design efforts. The implemented designs were compared using HLS tools and RTL designs in [6] and they found that 40% of the cases studied proved that HLS tools equaled or outperformed RTL designs from In terms of performance and better use of resources, they also studied whether the size of the design affects performance quality, and they concluded that HLS tools are suitable for both large and small designs. In paper [7] high level synthesis tool was used for implementing turbo decoder algorithms with exploration of HLS optimization using different directives for designing several archi-tecture designs of turbo decoders.…”

Section: Fig 1 General Block Diagram Of Digital Communication Systemsmentioning

confidence: 99%

Design Analysis of Turbo Decoder Based on One MAP Decoder Using High Level Synthesis Tool

Ali¹,

Alneema²

2020

(AREJ)

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High Level Synthesis (HLS) tool does not only simplify the designing operation and rapid prototyping but also allows the designers to explore large number of design's techniques such as parallelism, pipeline, memory partitioning and many other techniques. Turbo decoder based on Maximum APosterior Probability (MAP) algorithm is designed in this work using Vivado HLS. The normal turbo decoder with two MAP decoders were implemented with and without parallelism and proposed a new design of turbo decoder with one MAP decoder and it was designed with and without parallelism using different window technique in HLS tool which it is not explored previously. These designs were implemented for different frame size in this work. A comparison in latency and resource utilization where done and how a tradeoff done between these two parameters to reach the specific design that we need. The new design produces better results.

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Section: Fig 1 General Block Diagram Of Digital Communication Systemsmentioning

confidence: 99%

Design Analysis of Turbo Decoder Based on One MAP Decoder Using High Level Synthesis Tool

Ali¹,

Alneema²

2020

(AREJ)

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“…Estos métodos de entrada de diseño se han utilizado recientemente en una variedad de aplicaciones (por ejemplo, imágenes médicas, redes neuronales convolucionales y aprendizaje automático), con beneficios significativos en términos de rendimiento y consumo de energía [8] [9]. En [10] se presenta un relevamiento de experiencias de diseño HLS vs. RTL demostrando que esta nueva metodología permite obtener más rendimiento y un uso de recursos FPGA ligeramente menor, con un incremento considerable en la productividad, a costa de la pérdida de calidad de resultados (QoR).…”

Section: Introductionunclassified

Plataforma para Procesamiento de Imágenes sobre SoC FPGA de Xilinx

Medina

Leiva

Vázquez

2020

Elek.

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La aplicación de sistemas de procesamiento de imágenes en edge computing resulta cada vez más atractiva y necesaria. Sin embargo, las exigencias en cuanto a consumo de potencia y alto rendimiento impiden que puedan utilizarse plataformas de procesamiento estándares. En este aspecto, los FPGA son una buena opción para el desarrollo de sistemas de visión computacional a causa de su capacidad de explotación del paralelismo. Por otra parte, el flujo de diseño de las herramientas de síntesis de FPGA actuales admiten lenguajes de alta abstracción como descripciones de entrada, en contraposición a los lenguajes de descripción de hardware. La síntesis de alto nivel (HLS) automatiza el proceso de diseño al transformar la descripción algorítmica en hardware digital mientras se satisfacen las limitaciones del diseño. Sin embargo, a los expertos en procesamiento de imágenes puede resultarles compleja la integración hardware obtenida con el resto de los componentes del sistema, como por ejemplo interfaces de captura y visualización. En este trabajo, se presenta un diseño base para la construcción de aplicaciones de procesamiento de imágenes basada en Zynq. Se proporciona además una metodología que posibilita el desarrollo eficiente de soluciones de procesamiento de imágenes embebidas de manera ágil.

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“…Accurate estimates allow developers to optimize and rewrite their high-level code before compilation. However, the quality of the RTL specifications generated by the OpenCL compilers highly depends on the target platform and the quality of the high-level descriptions [15]. Indeed, the back-ends of the OpenCL compilers use metaheuristic algorithms, which tend to make them sensitive to the OpenCL input code.…”

Section: Introductionmentioning

confidence: 99%

“…To improve debugging and performance analysis capabilities, these instruments allow the observation of relevant values and accurate run-time analyses of any data in any section of the generated FPGA circuit. This instrumentation challenge is a known concern with hardware produced by HLS tools [15]. Indeed, timing performance analysis, hardware verification, and debugging capabilities can be performed with an assertion-based approach [19], such as the use ANSI-C assertions, enabling the instrumentation of the HLS-produced circuit [20].…”

Section: Introductionmentioning

confidence: 99%

In-FPGA Instrumentation Framework for OpenCL-Based Designs

2020

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The productivity achieved when developing applications on high-performance reconfigurable heterogeneous computing (HPRHC) systems is increased by using the Open Computing Language (OpenCL). However, the hardware produced by OpenCL compilers in field-programmable gate arrays (FPGAs) can result in severe performance bottlenecks that are challenging to solve. The problem is compounded by the fact that the generated netlist details are disorganized, making them mostly unreadable and only partially visible to designers. This paper proposes an in-FPGA instrumentation method and a new framework for extracting the FPGA-cycle-accurate timing performances of OpenCL-based designs. The results clearly show that the chosen execution model for OpenCL-based designs strongly affects the timing performance when it is not properly implemented. Our framework is implemented on an HPRHC platform that contains a CPU and two Arria10 FPGAs, and it is evaluated with a wide variety of benchmarks with different complexities. After testing on the reported benchmarks, the average logic overhead for one inserted instrument is 0.2 % of the total amount of adaptive look-up tables (ALUTs) and 0.1 % of the total registers in an FPGA. This resource utilization is between 1.5 and six times lower than those reported in the best previously published works. The scalability of the framework is also evaluated by inserting up to 50 instruments. The experimental results show that the average logic utilization per instrument is 0.19 % of the ALUTs and 0.17 % of the registers in the FPGA when 50 instruments are inserted.

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Are We There Yet? A Study on the State of High-Level Synthesis

Cited by 111 publications

References 60 publications

Design Analysis of Turbo Decoder Based on One MAP Decoder Using High Level Synthesis Tool

Design Analysis of Turbo Decoder Based on One MAP Decoder Using High Level Synthesis Tool

Plataforma para Procesamiento de Imágenes sobre SoC FPGA de Xilinx

In-FPGA Instrumentation Framework for OpenCL-Based Designs

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