Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA

Huddar, Sushma R.; Rupanagudi, Sudhir Rao; Janardhan, Venkatesh; Mohan, Surabhi; Sandya, S.

doi:10.1007/978-3-642-36321-4_45

Cited by 11 publications

(3 citation statements)

References 6 publications

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“…Though these methods provide better speeds, the computations involved are too complex, that they increase the on-chip area consumption. The Indian Mathematics, well known as Vedic Mathematics was revisited by Rupanagudi (Huddar S.R. et al,2013) and implemented a Vedic Mathematics multiplier on FPGA.…”

Section: Introductionmentioning

confidence: 99%

Design of 128-bit Complex Number Multipliers for Co-Processor

Panda¹

2020

Biosci. Biotech. Res. Comm

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Multipliers are the backbone of high-performance computing systems such as Microprocessors and Digital signal processors. Multipliers require more hardware resources and processing time, hence they are the slowest elements in the system. Multipliers are mainly used in today's high-end Digital Signal Processors and they occupy a larger chip area because of their inherent internal circuit complexity. Present-day co-processors are designed to support different size computations to achieve high performance. Researchers have worked on signed and complex number multipliers used in co-processors of 64 bit and below. There is a scope for designing a higher bit complex number multiplier to achieve higher performance. In this context, we proposed to design of 128-bit complex number multiplier of various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier using ModelSim SE 6.4 and Xilinx Vivado. In this work, various architectures such as Booth Multiplier, Modified Booth Multiplier, Urdhva Multiplier and Nikhilam Multiplier for 8-bit, 16-bit, 32-bit, 64-bit and 128-bit designed using Verilog for complex number multiplication. Nikhilam is one of the sutras of Vedic mathematics which is chosen for the implementation of complex number multiplier for area reduction. Synthesis reports are generated using the Xilinx Vivado tool for speed and power comparison. From the comparison, we have observed that Booth, Modified Booth, Urdhva, and Nikhilam occupy an area of 324.32%, 292.79%, 56.36%, and 46.70% respectively for 128-bit implementations. Among all the implemented methods, the Nikhilam method for complex number multiplier occupies very less area i.e. only 46.70% on-chip area.

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Section: Introductionmentioning

confidence: 99%

Design of 128-bit Complex Number Multipliers for Co-Processor

Panda¹

2020

Biosci. Biotech. Res. Comm

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“…The MAS (Multiplier Adder Subtractor) unit is incorporated [5] in the design of conventional ALU using Vedic Mathematics. The conventional ALU consists of Arithmetic Unit, Logic Unit and shifter module.…”

Section: Introductionmentioning

confidence: 99%

Implementation of N-Bit Binary Multiplication Using N - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Angeline¹,

Valarmathy²

2016

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This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N − 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N − 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.

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“…There are 6 steps where additions take place to produce the output. These additions can be performed in a pipelined manner to compute the final result [15]. It can be understood that the partial outputs are got by addition of the sub-partial outputs produced during single bit multiplication.…”

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confidence: 99%

Reversible logic in pipelined low power vedic multiplier

Eshack¹,

Krishnakumar²

2019

IJEECS

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With an ever growing demand for low-power devices, it is a general trend to search for ways to reduce the power consumption of a system. Multipliers are an important requirement in applications linked to Digital Signal Processing, Communication Systems, Optical Computing, Nanotechnology, Low-Power Very Large Scale Integration and Quantum Computing. Conventional mathematics makes multiplication a very long and time consuming process. The use of Vedic mathematics has led to great reduction in the time required for such calculations. The excessive use of Urdhava Tiryakbhyam sutra in multiplication surely proves its effectiveness and simplicity in this domain. This sutra supports the process of pipelining, a method employed in reduction of the power used by a system. Reversible logic has been gaining demand due to its low-power capabilities and is currently being used in many computing applications. The paper proposes two multiplier systems: one design employs the Urdhava Tiryakbhyam sutra along with pipelining and the second uses reversible logic gates into the first design. These proposed systems provide very less delay for result computation and low hardware utilization when compared to non-pipelined Vedic multipliers.

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Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA

Cited by 11 publications

References 6 publications

Design of 128-bit Complex Number Multipliers for Co-Processor

Design of 128-bit Complex Number Multipliers for Co-Processor

Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Reversible logic in pipelined low power vedic multiplier

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Area and Speed Efficient Arithmetic Logic Unit Design Using Ancient Vedic Mathematics on FPGA

Cited by 11 publications

References 6 publications

Design of 128-bit Complex Number Multipliers for Co-Processor

Design of 128-bit Complex Number Multipliers for Co-Processor

Implementation of &lt;i&gt;N&lt;/i&gt;-Bit Binary Multiplication Using &lt;i&gt;N&lt;/i&gt; - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method

Reversible logic in pipelined low power vedic multiplier

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Resources

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Implementation of <i>N</i>-Bit Binary Multiplication Using <i>N</i> - 1 Bit Multiplication Based on Nikhilam Sutra and Karatsuba Principles Using Complement Method