Area compact 5T portless SRAM cell for high density cache in 65nm CMOS

Yadav, Jitendra Kumar; Das, Pallavi; Jain, Abhinav; Grover, Anuj

doi:10.1109/isvdat.2015.7208095

Cited by 8 publications

(1 citation statement)

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“…The Fig 1 represents most frequently used electrical model of 6T-SRAM having the advantage comparatively with other designs. The advantage over 4T SRAM is treated as Load less model [2], 5T is treated as port less configuration [3] to reduce the total area of the design.…”

Section: Fig 1 6 T Sram Cell Of Electric Modelmentioning

confidence: 99%

Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

Reddy*,

Rao,

Reddy

2020

IJRTE

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With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.

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Section: Fig 1 6 T Sram Cell Of Electric Modelmentioning

confidence: 99%