Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution

Mukherjee, Paramita; D'souza, Sandeep; Chattopadhyay, Santanu

doi:10.1016/j.vlsi.2017.09.004

Cited by 4 publications

(2 citation statements)

References 45 publications

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“…There are many previous works addressing the synthesis of ASNoC topologies [9], [19]- [30]. However, these works rarely consider fault tolerance in the NoC topologies.…”

Section: Introductionmentioning

confidence: 99%

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Chen

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The Network-on-Chips based communication architecture is a promising candidate for addressing communication bottlenecks in many-core processors and neural network processors. In this work, we consider the generalized fault-tolerance topology generation problem, where the link (physical channel) or switch failures can happen, for application-specific network-onchips (ASNoC). With a user-defined maximum number of faults, K, we propose an integer linear programming (ILP) based method to generate ASNoC topologies, which can tolerate at most K faults in switches or links. Given the communication requirements between cores and their floorplan, we first propose a convexcost flow based method to solve a core mapping problem for building connections between the cores and switches. Second, an ILP based method is proposed to solve the routing path allocation problem, where K + 1 switch-disjoint routing paths are allocated for every communication flow between the cores. Finally, to reduce switch sizes, we propose sharing the switch ports for the connections between the cores and switches and formulate the port sharing problem as a clique-partitioning problem, which is solved by iteratively finding the maximum cliques. Additionally, we propose an ILP-based method to simultaneously solve the core mapping and routing path allocation problems when only physical link failures are considered. Experimental results show that the power consumptions of fault-tolerance topologies increase almost linearly with K because of the routing path redundancy for fault tolerance. When both switch faults and link faults are considered, port sharing can reduce the average power consumption of faulttolerance topologies with K = 1, K = 2 and K = 3 by 18.08%, 28.88%, and 34.20%, respectively. When considering only the physical link faults, the experimental results show that compared to the FTTG (fault-tolerant topology generation) algorithm, the proposed method reduces power consumption and hop count by 10.58% and 6.25%, respectively; compared to the DBG (de Bruijn Digraph) based method, the proposed method reduces power consumption and hop count by 21.72% and 9.35%, respectively.

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“…There are many previous works addressing the synthesis of ASNoC topologies [9], [19]- [30]. However, these works rarely consider fault tolerance in the NoC topologies.…”

Section: Introductionmentioning

confidence: 99%

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Chen

et al. 2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Authors in [10] present a thermal-aware floorplanner for slicing floorplan by modeling the temperature-dependent wire delay, routing congestion and reliability factors and including the same in addition to the chip area and temperature metrics in the cost function of the HotFloorplan tool. The work shown in [11] presents an Application Specific NoC synthesis approach involving floorplan which targets to optimize the chip area, peak on-chip temperature and communication cost. The algorithm has been developed in Mixed Integer Linear Programming and Simulated Annealing.…”

Section: Introductionmentioning

confidence: 99%

DOTFloor–A Diffusion Oriented Time-Improved Floorplanner for Macrocells

Choudhury

Pradhan

2019

IEEE Access

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This work presents a unique time-efficient and reliable floorplan algorithm DOTFloor (Diffusion Oriented Time-improved Floorplanner), built around a SA (Simulated Annealing) engine and targeted to optimize the peak on-chip temperature along with the traditional design metrics like chip area and wire length. This paper also proposes a novel heat-diffusion based stochastic thermal model called the FATT (Fast Assumption Technique for Temperature) which provides a fast assumption of the degree of hotness during the optimization process. The incorporation of FATT in DOTFloor results in a significant improvement in the run time of the optimization process. Upon experimentation on MCNC (Microelectronics Center of North Carolina) benchmark circuits with the proposed floorplanner, a good optimization in area, wire length metric and peak on-chip temperature with a significant reduction in execution time have been achieved over the existing floorplanning tool, the HotFloorplan.

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An Adaptive Symbiosis based Metaheuristics for Combinatorial Optimization in VLSI

Laudis¹,

Ramadass

Shyam³

et al. 2020

Procedia Computer Science

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Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution

Cited by 4 publications

References 45 publications

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips

DOTFloor–A Diffusion Oriented Time-Improved Floorplanner for Macrocells

An Adaptive Symbiosis based Metaheuristics for Combinatorial Optimization in VLSI

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