Area efficient and speed performance of pre encoded multiplier by using non redundant radix-4 signed digit encoding

Bhore, Chaitrali; Thakare, Rajesh

doi:10.1109/iceca.2017.8203686

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2020

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Section: Introductionmentioning

confidence: 99%

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Booth Algorithm with Implementation of UART Module using FPGA

Mahamad,

Sidek,

Saon

et al. 2020

IJIE

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FPGA gives high level of flexibility to the user to rapidly construct and test any hardware. It has a lot of gates which are used depending upon the hardware to be implemented. These project aims at designing Booth multiplier using VHDL for signed bit multiplication in FPGA for high speed operations, developed and implemented of UART module required to enable two-way communication between the DE-2 board and computer. It is also designed GUI interface using MATLAB for sending data and enable the output of the process result to be displayed. The Booth multiplier was implemented using the algorithm in both signed and unsigned number and the input and output of the multiplication was successfully achieved and confirmed through simulation. The GUI was implemented and tested, which UART module also performed well for transmitting and receiving of 8-bit width data. In general, the objective of this project was successfully achieved, which, the result of the component part were able to be tested.

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Section: Introductionmentioning

confidence: 99%

“…Multiplication operation mainly have three (3) stages. The first stage is generating the partial products, which generated through an array of AND gates.…”

Section: Introductionmentioning

confidence: 99%