Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

Ramesh, Chinthala; Murty, N. S.

doi:10.1109/iccci.2019.8822204

2019 International Conference on Computer Communication and Informatics (ICCCI) 2019

DOI: 10.1109/iccci.2019.8822204

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Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

Chinthala Ramesh

N. S. Murty

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Cited by 5 publications

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2021

2021 2nd Global Conference for Advancement in Technology (GCAT)

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Area Efficient Architecture for high speed wide data adders in Xilinx FPGAs

Cited by 5 publications

References 7 publications

Design and Analysis of Sobol Sequence Generator using gray code parallelization

Design and Analysis of Sobol Sequence Generator using gray code parallelization

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