Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Ghani, Arfan; McGinnity, T.M.; Maguire, Liam; Harkin, Jim

doi:10.1109/fpl.2006.311352

Cited by 16 publications

(14 citation statements)

References 3 publications

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“…For an area-efficient implementation of a neural reservoir on reconfigurable hardware, it is necessary that the use of area hungry operators such as multipliers are minimised or completely avoided [13,14]. In traditional modelling of synapses, inputs are multiplied with fixed weights and because of this multiplication the number of multipliers increases with an increased number of synapses.…”

Section: Reconfigurable Architecture For Reservoir Implementationmentioning

confidence: 99%

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Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

Ghani

See

Ali

2014

IET Science, Measurement & Technology

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This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform -field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation.

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Section: Reconfigurable Architecture For Reservoir Implementationmentioning

confidence: 99%

“…It exploits previously published techniques, namely area efficient multiplier-less architecture, which overcomes the burden of multipliers required for synaptic multiplications [13,14]. To investigate the viability of implementing RC paradigm on HW/SW platform, this work presents area efficient spiking neurons architectures.…”

Section: Introductionmentioning

confidence: 98%

Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

Ghani

See

Ali

2014

IET Science, Measurement & Technology

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“…Several authors have examined the acceleration of neural network processing through FPGAs [20][21][22][23], customintegrated circuits [24], and parallel computation [13]. The FPGA designs in Refs.…”

Section: Related Workmentioning

confidence: 99%

“…[21][22][23] implemented feedforward fully connected neural networks, while the design we implement is a Baysian network that operates through both feed-forward and feed-back belief propagations. Ghani et al [21] proposed a multiplier-less circuit for spiking neural networks. Their design is very area efficient, and allows large-scale FPGA-based implementations of spiking neural networks.…”

Section: Related Workmentioning

confidence: 99%

Hardware acceleration of image recognition through a visual cortex model

Rice

Taha

Vutsinas

2008

Optics & Laser Technology

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“…The ability to reconfigure FPGA logic blocks and interconnect has attracted researchers to explore the mapping of SNNs to FPGAs [5][6][7][8][9]. Efficient, low-area/power implementations of synaptic junctions and neuron interconnect are key to scalable SNN hardware implementations.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network‐On‐Chip and Spiking Neural Networks

Harkin

Morgan

McDaid

et al. 2009

International Journal of Reconfigurable Computing

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FPGA devices have emerged as a popular platform for the rapid prototyping of biological Spiking Neural Networks (SNNs) applications, offering the key requirement of reconfigurability. However, FPGAs do not efficiently realise the biologically plausible neuron and synaptic models of SNNs, and current FPGA routing structures cannot accommodate the high levels of interneuron connectivity inherent in complex SNNs. This paper highlights and discusses the current challenges of implementing scalable SNNs on reconfigurable FPGAs. The paper proposes a novel field programmable neural network architecture (EMBRACE), incorporating low-power analogue spiking neurons, interconnected using a Network-on-Chip architecture. Results on the evaluation of the EMBRACE architecture using the XOR benchmark problem are presented, and the performance of the architecture is discussed. The paper also discusses the adaptability of the EMBRACE architecture in supporting fault tolerant computing.

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Area Efficient Architecture for Large Scale Implementation of Biologically Plausible Spiking Neural Networks on Reconfigurable Hardware

Cited by 16 publications

References 3 publications

Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

Hardware acceleration of image recognition through a visual cortex model

A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network‐On‐Chip and Spiking Neural Networks

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