Area-Efficient Design of Modular Exponentiation Using Montgomery Multiplier for RSA Cryptosystem

Nti, Richard Boateng; Ryoo, Kwangki

doi:10.1007/978-981-13-1328-8_56

Cited by 6 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Refs. [10,24] achieve a higher frequency by applying a customized CSA design, but their design require more cycles to complete more iterations, and finally cannot achieve higher performance and ATP value. Ref.…”

Section: Results and Comparisonsmentioning

confidence: 99%

“…In comparison with (2),we can get a cycle_ratio in (10). Previously, we have mentioned that the whole operand cannot be read or written only in one cycle, which will also inevitably impact basic RBR-MMM.…”

Section: Timing Analysismentioning

confidence: 99%

“…Previously, we have mentioned that the whole operand cannot be read or written only in one cycle, which will also inevitably impact basic RBR-MMM. Thus the loop_ratio will be smaller than (10) in hardware design.…”

Section: Timing Analysismentioning

confidence: 99%

“…Digital-serial implementations are proposed using high radix MMM, such as a radix-4 architecture using lookup tables [6] or booth encoding [7]. Radix-8 architecture uses booth encoding [8] and typically improves schemes based on carry-save adder (CSA) for the radix-2 system [9,10]. Some optimization has also been made on the CSA architecture [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

Zhaoji

Zhang

2022

Electronics

View full text Add to dashboard Cite

The Montgomery modular multiplication is an integral operation unit in the public key cryptographic algorithm system. Previous work achieved good performance at low input widths by combining Redundant Binary Representation (RBR) with Montgomery modular multiplication, but it is difficult to strike a good balance between area and time as input bit widths increase. To solve this problem, based on the redundant Montgomery modular multiplication, in this paper, we propose a flexible and pipeline hardware implementation of the Montgomery modular multiplication. Our proposed structure guarantees a single-cycle delay between two-stage pipeline units and reduces the length of the critical path by redistributing the data paths between the pipelines and preprocessing the input in the loop. By analyzing the structure and comparing the related work in this paper, our structure ensures a lower area-time product while achieving a controllable and small area consumption. The comprehensive results under different Taiwan Semiconductor Manufacturing Company (TSMC) processes demonstrate the advantages of our structure in terms of flexibility and area-time product.

show abstract

Section: Results and Comparisonsmentioning

confidence: 99%

Section: Timing Analysismentioning

confidence: 99%

Section: Timing Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

Zhaoji

Zhang

2022

Electronics

View full text Add to dashboard Cite

show abstract

“…The serial structure [2,7,8,9,10,11] scans the multiplier bit by bit, leading to low area complexities. However, the cycle cost of serial multipliers are much higher than fullword multipliers.…”

Section: Introductionmentioning

confidence: 99%

FPGA-based high-throughput Montgomery modular multipliers for RSA cryptosystems

Xiao

Cheng

et al. 2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents an FPGA-based Montgomery modular multiplier for implementing high-throughput RSA cryptosystems. First, we propose a variable segmentation Montgomery modular multiplication (VS-MMM) algorithm which enables the radix of the multiplier and the multiplicand adapt to any given datawidth. Then, to make trade-offs among latency, area and throughput, we design a dual-path fully concurrent MMM architecture based on VSMMM algorithm. As a case study, a RSA processor has been implemented using the proposed method. Experimental results show that the proposed MMM multiplier and RSA processor achieve much higher throughput than existing works.

show abstract

Implementing Montgomery Multiplication to Speed-Up the Computation of Modular Exponentiation of Multi-Bit Numbers

Prots’ko,

Gryshchuk

2024

Cybern Syst Anal

View full text Add to dashboard Cite

Area-Efficient Design of Modular Exponentiation Using Montgomery Multiplier for RSA Cryptosystem

Cited by 6 publications

References 7 publications

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

FPGA-based high-throughput Montgomery modular multipliers for RSA cryptosystems

Implementing Montgomery Multiplication to Speed-Up the Computation of Modular Exponentiation of Multi-Bit Numbers

Contact Info

Product

Resources

About