Area efficient folded undecimator based ECG detector

Abstract

This paper presents an area-efficient folded wavelet filter-based Electrocardiogram (ECG) detector for cardiac pacemakers. The modified folded undecimator based detector consists of Wavelet Filter Bank, QRS complex detector with Generalized Likelihood Ratio Test (GLRT) block and noise detector. A high-level transformation technique such as folding transformation and Cutset retiming are applied to the GLRT block in order to reduce the silicon area. Folding is a high-level transformation applied at the architectural level to enhance the performance of DSP architectures. It reduces the number of adders, multipliers and delay elements in the architecture. The Cutset retiming reduces clock period of the architecture by changing position of delay elements in the critical path. The folding transformation and cutset retiming implement the functional blocks of the GLRT circuit with minimum hardware. The modified folded ECG detector is tested for short term and long-term MIT-BIH databases. The results show that the modified folded undecimator detector has hardware savings and achieves sensitivity of 99.95%, positive prediction of 99.97% and Detection Error Rate (DER) of 0.061. The folded GLRT block architecture is synthesized with FPGA Zed board XC7Z010CLG484-1. Results show that the device utilization and power consumption are lesser than the conventional GLRT structure.

Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector

“…Few works in the literature so far have discussed designing area and power-efficient health monitoring devices, such as ECG detectors. Authors in 3 present a high level transformations (HLTs) based design of ECG detector. Authors in 3 have used folding and cutset retiming (CTR) HLTs on the GLRT architecture of the ECG detector to obtain an area-efficient ECG hardware design.…”

“…Authors in 3 present a high level transformations (HLTs) based design of ECG detector. Authors in 3 have used folding and cutset retiming (CTR) HLTs on the GLRT architecture of the ECG detector to obtain an area-efficient ECG hardware design. Folding helps in reducing the multipliers, adders, and delay elements, while CTR helps in reducing the architecture's clock period by altering the delay element's position in the critical path.…”

“…Folding helps in reducing the multipliers, adders, and delay elements, while CTR helps in reducing the architecture's clock period by altering the delay element's position in the critical path. Authors performed FPGA synthesis of the modified architecture to execute the testing process 3 . The presented approach in 3 facilitates the generation of the area and power-efficient design of ECG detectors using folding and cutset retiming.…”

“…Authors performed FPGA synthesis of the modified architecture to execute the testing process 3 . The presented approach in 3 facilitates the generation of the area and power-efficient design of ECG detectors using folding and cutset retiming. However, it is incapable to design secure RTL datapath of micro GLRT and GLRT cascade macro hardware IP core for ECG detector using the HLS framework, having immunity against IP piracy and fraudulent claim of IP ownership threats, like in the proposed approach.…”

“…ECG detector comprises of various critical components that perform crucial functions such as GLRT unit, filtering unit, analog to digital converter unit, etc. 3 . GLRT unit is the primary component of the ECG detector that executes computation-intensive functions to estimate heart rate using (Q wave, R wave and S wave) QRS wave complex from incoming filter signals.…”