Area Efficient High Speed and Low Power MAC Unit

Abstract

With the growing importance of electronic products in day-today life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit the carry save adder(CSA), carry select adder(CSLA) and carry skip adder(CSKPA) are also used instead of CLA to compare the power and performance. These MAC designs were simulated and synthesized using Xilinx 8.1. The simulation result shows that the MAC design with CLA has area reducing by 16.7%, speed increase by 1.95% and the consumed power reducing by 0.5%.

Design and Analysis of Multiplier Accumulator Circuit for DSP Applications

“…CLA consists of two logic blocks, Partially Full Adder (PFA) and Carry Look Ahead logic (CLA logic). Each PFA has two outputs Pi and Gi given to CLA logic, and one carry input Ci from the CLA logic to each PFA [12]. When compared to other adders, it outperforms them in terms of power consumption and gate count resulting in reduction in area utilized.…”