Area efficient implementation of FSK receiver on Xilinx Zynq FPGA

Reddy, T. Thammi; Madhavi, B. K.; Kishore, K. Lal

doi:10.1109/inventive.2016.7823202

2016 International Conference on Inventive Computation Technologies (ICICT) 2016

DOI: 10.1109/inventive.2016.7823202

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Area efficient implementation of FSK receiver on Xilinx Zynq FPGA

T. Thammi Reddy

B. K. Madhavi²,

K. Lal Kishore

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2018

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“…The FSK Demodulator has blocks Spectrum shifting, Decimation, DDC, Complex multiplication, Symbol filtering, Magnitude computation and Decision device. The FSK Demodulator is explained in the paper(Reddy et al, 2016) more clearly.…”

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confidence: 99%

Area efficient SDR receiver without and with dynamic partial reconfiguration

Reddy

Madhavi²,

Kishore

2018

IJISTA

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Dynamic partial reconfiguration (DPR) technique is a very efficient for low-cost field programmable gate array (FPGA) for realising several application categories like signal processing. The present work demonstrates a generic framework for implementing Software Defined Radio (SDR) based communication system using DPR. The work switches contexts with two partial reconfiguration blocks. Namely spectrum estimation and frequency shift keying (FSK) receiver blocks. The former uses the streaming type fast Fourier transform (FFT) and later uses frequency shifting and filtering stages. The completely developed FSK receiver is simulated using Modelsim. Xilinx Zynq 7010 SoC with DPR is used for implementation. An FSK signal with symbol rate 64 Kbps is used to drive the analogue to digital converter (ADC) input. The work demonstrates novel direction for SDR implementation with DPR for low-area FPGAs. The results shows 45% lesser FPGA-DSP48 slices are used compared to without-DPR. Reduced power dissipation is observed as byproduct.

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confidence: 99%

Area efficient SDR receiver without and with dynamic partial reconfiguration

Reddy

Madhavi²,

Kishore

2018

IJISTA

Self Cite

View full text Add to dashboard Cite

show abstract

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Area efficient implementation of FSK receiver on Xilinx Zynq FPGA

Cited by 1 publication

References 5 publications

Area efficient SDR receiver without and with dynamic partial reconfiguration

Area efficient SDR receiver without and with dynamic partial reconfiguration

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