Area-efficient reed-solomon decoder design for optical communications

Abstract

A high-speed low-complexity Reed-Solomon (RS) decoder architecture based on the recursive degree computationless modified Euclidean (rDCME) algorithm is presented in this brief. The proposed architecture has very low hardware complexity compared with the conventional modified Euclidean and degree computationless modified Euclidean (DCME) architectures, since it can reduce the degree computation circuitry and replace the conventional systolic architecture that uses many processing elements (PEs) with a recursive architecture using a single PE. A highthroughput data rate is also facilitated by employing a pipelining technique. The proposed rDCME architecture has been designed and implemented using SMIC 0.18-μm CMOS technology. Synthesized results show that the proposed RS (255, 239) decoder requires only about 18K gates and can operate at 640 MHz to achieve a throughput of 5.1 Gb/s, which meets the requirement of modern high-speed optical communications.

Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems

“…Excluding the control block, the proposed FME architecture consists of 4 FFMs, 2 FFAs, 60 registers, and 4 multiplexers. In Table 2, although the designs in [3], [4], and [6] have better TC than ours because of the use of pipelined multipliers, the proposed FME architecture has the lowest AC and the smallest AT complexity. Compared with design in [5], ours has small AC and TC, respectively, because fewer registers are required for storing the coefficients of updated polynomials and a shorter critical path delay exists in the proposed design.…”

“…Compared with design in [5], ours has small AC and TC, respectively, because fewer registers are required for storing the coefficients of updated polynomials and a shorter critical path delay exists in the proposed design. The design in [6] takes 260 clock cycles for solving the key equation. This implies that the performance of the decoder is degraded because the decoding delay of the KES unit is more than 255.…”

“…However, the architecture is not cost-effective and requires a larger number of clock cycles to solve the key equation. In recent years, three area-efficient folded architectures developed using the ME algorithm have been presented [4]- [6]. In [4], Lee employed the pipelined recursive method to obtain a high throughput rate.…”

“…The basic idea of the design in [5] is to use a pre-computation method to eliminate the idle time of the KES unit; the hardware cost is reduced by employing folding techniques. Based on Lee's work, the authors in [6] removed the need for the degree computation circuit and shortened the critical path delay.…”

“…To reduce hardware complexity, an efficient polynomial manipulation scheme based on our previous work [20] is presented to remove redundant information in the polynomial representation of the TME algorithm. Applying the boundary cell simplification and folding techniques, the proposed RS(255,239) decoder obtains a 36 % reduction in hardware requirement and has a better area-time complexity compared to those in [6]. Experimental results show that the proposed RS(255, 239) decoder can operate at up to 425 MHz with a total gate count of 11,759 based on the TSMC 0.18 μm process.…”