Area-Efficient Scheduling Scheme Based FFT Processor for Various OFDM Systems

Jang, Jeong Keun; Kim, Ho Keun; Sunwoo, Myung Hoon; Gustafsson, Oscar

doi:10.1109/apccas.2018.8605617

Cited by 9 publications

(2 citation statements)

References 13 publications

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“…LTE also uses advanced coding techniques such as Turbo codes, convolutional codes, and LDPC codes to improve the performance. These enable LTE to give higher data rates with lower error rates [11].…”

Section: Traditional Lte Systemmentioning

confidence: 99%

Enhancement of BER of LTE System by Using DCT-Neural Network in Different Channel Models

Ahmed,

Al-Thahab

2024

MMEP

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In this work the discrete cosine transform is proposed for LTE systems with the aid of feed-forward neural network as a suitable equalizer to retrieve the effect of channel within Rayleigh Faded channels. This system was implemented using the Quadrature-Phase Shift Keying as a modulation technique, and using different Maximum Doppler Shift, which represents the highest Doppler shift that can occur between the transmitter and the receiver in a given wireless channel. by using DCT-FFNN with different MDS values effectively mitigates signal distortion resulting from multipath propagation and common issues in wireless communication networks and demonstrates higher accuracy in predicting BER values. According to the research, the performance will be better at MDS 50 when compared to the rest of the MDS used in the paper. These advantages come with minimal loss in data rate and bandwidth and no additional expense in terms of power. The simulation results indicate that an FFNNs-based channel estimator outperforms the pilot-based channel estimator in LTE systems operating over a Rayleigh fading channel, because FFNNs have low complexity and can quickly and accurately adjust the signal strength of incoming signals based on their input. All LTE system models were implemented using MATLAB 2016.

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Section: Traditional Lte Systemmentioning

confidence: 99%

Enhancement of BER of LTE System by Using DCT-Neural Network in Different Channel Models

Ahmed,

Al-Thahab

2024

MMEP

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“…Another approach to reduce the latency in both memory-based and pipelined FFTs is to increase the parallelization of the architecture. In fact, this approach has been widely used for pipelined FFTs, where highly parallel [15], [16], [17], [18], [19] and fully-parallel [20], [21], [22] FFT architectures have been presented. Nevertheless, the area of these architectures is extremely large.…”

Section: Introductionmentioning

confidence: 99%

Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G

Kaya,

Garrido

2023

IEEE Trans. Circuits Syst. I

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This paper presents a novel 64-parallel 4096-point radix-2 memory-based fast Fourier transform (FFT) architecture for 6G. This approach is the first one to use 64 parallel branches in memory-based architectures. The challenge of designing a memory-based FFT with such a high parallelization has been accomplished by paying special attention to the large number of memories in parallel. Their control has been simplified by using the same read and write address for all of them thanks to the perfect shuffle permutation, and they are organized in groups to eliminate unnecessary registers. Likewise, a novel design for the rotation memories allows for reusing rotation coefficients among parallel rotators, and a new design for the circular counter that controls the architecture is presented. The proposed FFT architecture has been implemented on a Virtex 7 field-programmable gate array (FPGA). Experimental results reveal that the proposed architecture achieves the lowest latency in clock cycles and the highest throughput in samples per clock cycle among memory-based FFT architectures so far.

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Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

Moni Varghese,

Sundaram

2024

Circuit Theory & Apps

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Designing FFTs with higher radix butterfly units are increasingly in demand to combat the high throughput of 20 Gbps of the current 5G and 1 Tbps for beyond 5G technologies. Previous higher radix FFTs were implemented in FPGA, giving importance to area and power. This paper presents the design of radix‐power‐of‐2 butterfly circuit, using the proposed radix cosine coefficients' extractor equation that is applicable to all the inputs. This enables efficient pipelined shift‐add implementation of the required complex rotations. The proposed methodology encompasses the implementation of any power‐of‐two‐radix butterfly to realize large size FFT, essential for real‐time 5G and 6G applications. The proposed radix‐4, radix‐8, radix‐16, and radix‐32 architectures are implemented and verified on Xilinx Spartan‐7 FPGA using Vivado Design Suite (v2018). The results demonstrate that the proposed radix‐16 and radix‐32 architectures achieve a higher clock frequency, by a factor of 5.23 and 6.76, respectively, compared to the most recent literature. For performance analysis, the area‐delay and power‐delay products of the proposed radix‐16 and radix‐32 butterfly architecture are computed. The proposed radix‐16 butterfly architecture exhibits a 13.3% reduction in area‐delay product and a 34.25% decrease in power‐delay product compared to recent literatures. Similarly, the radix‐32 architecture shows a 27.31% lower area‐delay product and a 0.63% lower power‐delay product.

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Area-Efficient Scheduling Scheme Based FFT Processor for Various OFDM Systems

Cited by 9 publications

References 13 publications

Enhancement of BER of LTE System by Using DCT-Neural Network in Different Channel Models

Enhancement of BER of LTE System by Using DCT-Neural Network in Different Channel Models

Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G

Design of High‐Performance Radix‐Power‐of‐2 Butterfly Architectures for FFT Implementation by Cosine Coefficients Extraction

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